A Capability → Investment Study of China's Semiconductor Stack
June 2026
A capability → investment study of China’s semiconductor industry. Drafted, edited, and illustrated by three sequential 10-agent research fleets over a 1,029-finding knowledge base spanning US/Western and mainland-China/Taiwan sources (2023–2026).
Every factual claim carries an inline citation in the form source · F⟨id⟩, where F⟨id⟩ is a finding in the underlying knowledge base. ~41,000 words · 802 inline citations · 398 unique findings · 13 charts. English-only; where the source is Chinese it is glossed.
June 2026. Source documents: D1–D10 in this directory. Inline markers like TechInsights · F4 cite a source and a knowledge-base finding ID; “(D7)” points to the deep dive with the full treatment.
China will not build a leading-edge logic chip this decade — but the export-control regime that guarantees that has also handed China a captive, state-funded localization market worth well over USD 150 billion, and China is already winning, on price, in every part of the industry that does not require EUV lithography. The bear case (advanced logic is capped) and the bull case (everything else is opening) are both true at once, and the investable conclusion follows from holding them together rather than choosing one.
Strip the industry to its physics and a single fact organizes everything. A chip is designed, then printed on a wafer, then packaged and tested. China is competitive at the design front-end and the packaging back-end, and gated in the middle — at the wafer fab — by the extreme-ultraviolet (EUV) scanner that only ASML builds and that no rule has ever let into China (D1). The proof is on the teardown bench: SMIC’s best process, the “N+3” in Huawei’s late-2025 Kirin 9030, measures ~113 MTr/mm² — TSMC 6/7nm-class, one to two generations behind the frontier, achieved with deep-ultraviolet (DUV) multipatterning at 40–50% higher cost and yields as low as 20–33% (SemiAnalysis · F77; AEI · F100) (D1). The next transistor architecture (gate-all-around, for 2nm) needs EUV too, so the denial forecloses not one node but the whole generation beyond (D1).
The pattern repeats at every layer: anything that needs sub-7nm lithography is gated; anything that does not is amber-to-green. That is the map.
In the EUV-immune families, China is not catching up; it is leading and using price as a weapon.
The catch (D7, D10): this is share-now, margin-later. The same price war that bankrupted Wolfspeed pushed China’s own leader SICC to a net loss. The binding risk in the winning segments is financial endurance, not capability.
Huawei’s Ascend is the frontier, and two facts define it. First, its most advanced 2024–25 output ran on ~2.9M illicitly-routed TSMC dies (via the Sophgo shell), now exhausted — future Ascend depends entirely on SMIC wafers plus domestic HBM (D2). Second, per chip the 910C is ~60% of an H100; Huawei closes the gap by brute force (CloudMatrix 384 ≈ 1.7× a GB200 NVL72, at 4.1× the power) (D2). But the more durable constraint is software (D8): China’s six-plus incompatible compute stacks (CANN, MUSA, MACA, NeuWare, DTK, IXUCA) cannot pool the network effects of one CUDA, and the state’s answer — forcing unification via BAAI’s FlagOS and Baidu’s PaddlePaddle — is, paradoxically, accelerated by the very export controls that push developers off CUDA.
Demand is real and concentrated: China’s accelerated-server market doubled to ~USD 16B in H1 2025 and is headed past USD 140B by 2029, ~69% of it four hyperscalers (IDC via iTiger · F854). The state chequebook is unmatched — Big Fund III at RMB 344B (~USD 47.5B) is larger than Phases I and II combined and aimed squarely at the bottlenecks (litho, photoresist, HBM, packaging) (中证网 · F708) — but it carries a real caveat: prior phases produced both winners and a graft probe plus the ~USD 19B Wuhan Hongxin zombie-fab fraud (D9). And China holds one chokepoint of its own: ~98% of refined gallium, ~68% of germanium, the leverage it spent to win the EDA reversal (D4, D6).
Rank by exposure × purity — how structural the localization tailwind is, times how cleanly a listed equity captures it.
Read the dives for the fully-sourced detail: D1 lithography · D2
AI compute · D3 memory/HBM · D4 export controls · D5 equipment/metrology
· D6 materials/leverage · D7 where China is winning · D8 software moat ·
D9 capital/demand/state · D10 investment thesis. The underlying
knowledge base holds 1,029 source-attributed findings; query any
F-number with scripts/kb detail <n>.
Lithography is the single hardest chokepoint in China’s drive for semiconductor self-sufficiency, and it sets a ceiling on how advanced a logic chip the country can build at commercial volume. The constraint is physical: the wavelength of the light used to expose a wafer bounds how small a feature it can print, and China is locked out of the one tool that the rest of the leading edge depends on — extreme-ultraviolet (EUV) lithography. Cut off from EUV, China’s flagship foundry SMIC has reached a “7nm-class” node — and, by late 2025, an incremental “N+3” carried into the Huawei Mate 80’s Kirin 9030, plus 5nm pilot runs aiming at mass production in 2026 — by pushing older deep-ultraviolet (DUV) tools far past their intended limits (techpowerup · F1091). The result is real advanced logic, as the Huawei Mate 60 Pro’s Kirin 9000S proved (TechInsights · F4). But it comes at yields reported as low as 20-40 percent, costs 40-50 percent above TSMC, and a density closer to TSMC’s 7nm than to a true 5nm node (SemiAnalysis · F77, AEI · F100, TechInsights · F1162). This document walks through the physics, the toolchain monopoly, China’s indigenous attempts, the SMIC node ladder as read from phone teardowns, why “SMIC 7nm” is not “TSMC 7nm,” and the second wall waiting at 2nm and gate-all-around transistors.
Figure 1 — Measured by transistor density, SMIC’s best logic node
(N+3, 113.4 MTr/mm²) sits just above TSMC’s 6nm and one to two full
generations behind TSMC’s EUV nodes. Source: SemiAnalysis
· F77.
Lithography prints circuit patterns by shining light through a mask onto a light-sensitive coating on a silicon wafer. The smallest feature it can resolve follows the Rayleigh equation, resolution = k1 · λ / NA, where λ is the light’s wavelength, NA is the lens’s numerical aperture (its light-gathering angle), and k1 is a process constant. Shrinking λ is the most direct lever. The industry’s workhorse DUV tools use an argon-fluoride (ArF) excimer laser at a 193nm wavelength (Wikipedia/SMEE · F5). EUV machines drop to 13.5nm — roughly a 14-fold shorter wavelength — which is why a single EUV exposure can directly print features that 193nm light cannot.
When you cannot shrink the wavelength, you fake the resolution with multipatterning: split one dense layer into several coarser exposures and etch them together, using techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP, four exposures per critical layer). This works, but it multiplies the steps and the chances for misalignment. A 7nm logic chip built on DUV runs more than 80 lithography steps in total, with roughly a dozen critical layers doubled or quadrupled (AEI · F100, AEI · F294). Counting only the critical layers, the most-cited shorthand is that 7nm on DUV reportedly needs about 34 lithography passes where EUV needs about 9 (EDN · F244). Chinese fabs are estimated to burn 1.5 to 2 times the ArF-immersion (ArFi) scanner hours per wafer that TSMC spends using EUV (AEI · F100). Every extra exposure is another chance for a defect — the root of the yield problem discussed in Section 6.
Exactly one company on Earth ships EUV scanners: ASML of the Netherlands, which holds a complete monopoly on EUV and roughly 90 percent of global DUV-immersion shipments (AEI · F291); ASML still holds 100 percent of EUV and about 83 percent of total lithography sales in 2025, with Nikon and Canon confined to older KrF and i-line tools (eeNews · F1154). ASML has never shipped a single EUV machine to China (TrendForce · F304), and it reaffirmed as much in mid-2026: on 19 June 2026 US Commerce Secretary Howard Lutnick reportedly told ASML executives of concerns that a top-tier EUV machine may have ended up in China, but CEO Christophe Fouquet flatly denied any such machine exists or ever has in China, noting ASML tracks every machine it ships and an internal firewall keeps China-based staff away from EUV technology (TechCrunch · F1077). The scanner is not one supplier’s product. Its hardest-to-replicate subsystem is the optics — mirrors that collect and project 13.5nm light to nanometer precision — supplied near-monopolistically by Zeiss SMT of Germany. Zeiss states that its High-NA EUV optics have no sales even within Germany outside ASML, which cuts China off from the core optics for advanced nodes; ASML’s EUV light source additionally depends on high-power CO2 lasers from TRUMPF of Germany (Zeiss SMT · F305).
The chokepoint extends past the scanner into consumables. EUV mask blanks — low-thermal-expansion glass coated with 40-50 alternating silicon/molybdenum layers — are supplied commercially only by AGC and Hoya of Japan; that market was about 194 million USD in 2024, projected to reach roughly 551 million USD by 2032 (IntelMarketResearch · F306). Photoresists, the light-sensitive coatings, are another foreign-held bottleneck. Per a 2024 SDIC Securities report, China’s KrF resist self-sufficiency is under 5 percent and ArF under 1 percent, with the global market dominated by six Japanese and US majors (JSR, Tokyo Ohka, DuPont/Rohm-Haas, Shin-Etsu, Sumitomo, Fujifilm) (SDIC Securities · F409). Chinese firms are climbing this ladder: Tongcheng New Materials reached ArF mass-production capability and booked H1-2024 photoresist revenue of 128 million RMB, up 54 percent year-on-year, and Nata Opto has three validated ArF resists in small-volume sales (Tongcheng · F411, JW Insights · F424). But those ArF-immersion resists target 28nm and above, not the leading edge.
Because China can buy DUV but not EUV, its dependence on ASML’s DUV-immersion fleet is enormous: Chinese entities accounted for 70 percent of ASML’s DUVi tool sales in 2024 (CNAS · F16, AEI · F291). Total ASML sales to China in 2024 reached nearly 12 billion USD, more than a third of company revenue (AEI · F291). The controls have tightened in steps, and each step triggered a buying rush ahead of it:
| Date | Action | Tools captured | Source |
|---|---|---|---|
| 30 Jun 2023 (eff. 1 Sep 2023) | Netherlands requires licenses for top DUVi models | NXT:2000i, 2050i, 2100i; NXT:1980i still allowed | Reuters/TrendForce · F37 |
| 17 Oct 2023 | US BIS bans tools with chuck overlay 1.5-2.4nm | NXT:1980Di (1.6nm), NXT:1970Ci (2.0nm) | Asia Times · F41 |
| Sep 2024 | Netherlands adds 1970i/1980i; brings servicing/parts/software under license | NXT:1970i, 1980i + servicing of restricted tools | TrendForce · F46 |
| Dec 2024 | US BIS targets node-agnostic tools and DUV “jailbreak” software | multipatterning-enabling software configurations | AEI · F97 |
| 1 Apr 2025 | Netherlands shifts license-filing for certain ASML tools and Dutch metrology/inspection gear from US to Dutch authority | additional DUV + Dutch metrology/inspection | AEI/AI Policy · F1180 |
| Apr 2026 (proposed) | MATCH Act introduced in US House (2 Apr), cleared committee markup (22 Apr) | would ban even DUV-immersion sales to Chinese chipmakers + bar servicing | Asia Times · F1074 |
The stockpiling these controls provoked is visible in customs data. China’s total lithography-machine imports hit 8.74 billion USD in 2023, 83 percent from the Netherlands; cumulative Dutch imports came to 7.23 billion USD (225 units at a 32.13 million USD average unit price), up 184 percent year-on-year, with July 2023 Dutch imports up nearly eight-fold (Jiemian/customs · F470). ASML’s own China revenue jumped from more than 6.4 billion EUR (29 percent of revenue) in 2023 to about 10.2 billion EUR (36 percent) in 2024 (ASML/customs · F303). The momentum carried into early 2024: even after the January 2024 tightening, Jan-Feb 2024 still saw 1.06 billion USD (32 units) of Dutch litho imports, with total litho import value up 256 percent year-on-year (Jiemian/customs · F476). Across all top-five allied suppliers, Chinese firms bought 38 billion USD of equipment in 2024, up 66 percent versus 2022 (CNAS · F27).
In capacity terms, AEI estimates that of ASML’s 374 DUV machines shipped globally in 2024, 129 were ArF-immersion systems, and SMIC and its peers likely acquired close to 90 of them, worth roughly 5-7 billion USD; an NXT:1980Fi prints 275-330 wafers per hour with a ceiling near 2.4 million passes per year, so about 90 machines could sustain several million 7nm-class wafer starts (AEI · F290). Servicing is the most important lever the controls have not yet pulled. ASML DUVi tools need maintenance roughly every six months; analysts estimate that cutting off servicing would significantly degrade China’s fleet within a single year, while continued servicing extends tool lifespans toward 30 years (CNAS · F30). AEI’s recommended fix is capability-based controls, a countrywide presumption of denial, and servicing restrictions (AEI · F295).
By early 2026 the stockpiling boom had unwound sharply. ASML shipped 327 lithography systems in 2025, down from 418 in 2024, with the decline concentrated in fewer DUV shipments to China (eeNews · F1154). In Q1 2026, China fell to just 19 percent of ASML’s net system sales — down from 36 percent in Q4 2025 — as Dutch DUV controls and the stockpiling reversal bit, and South Korea (driven by Samsung and SK Hynix EUV orders) overtook China as ASML’s largest market at 45 percent; ASML still ships zero EUV to China (Bloomberg · F1064). The policy gap that enabled the loophole remains, however: as of April 2026 the Dutch controls stay country-neutral and case-by-case rather than a blanket China ban, so as many as 41 Chinese companies still held valid licenses to import ASML DUV machines, and ASML sold nearly 3 billion USD of equipment and services to Chinese entities of concern in 2024 (AEI/AI Policy · F1180). The fix policy analysts want is exactly what the MATCH Act, introduced in the US House on 2 April 2026 and cleared through a House Foreign Affairs Committee markup on 22 April, would attempt: ban even ASML DUV-immersion sales to Chinese chipmakers, force the Netherlands and Japan to align within 150 days, and bar servicing and upgrades of machines already in China — though by mid-April the bill was reportedly being scaled back, the Trump administration had taken no formal position, and the Dutch government opposed it (Asia Times · F1074). ASML’s service business makes this lever bite: Installed Base Management revenue was 2.5 billion EUR in Q1 2026 alone, a recurring stream that puts the servicing-license chokepoint at the center of the fight (eeNews · F1154).
China’s national lithography champion, SMEE (Shanghai Micro Electronics Equipment), is roughly two decades behind the leading edge. Its most advanced front-end tool before 2023, the SSA600 series, is a 193nm ArF-immersion scanner capable only of 90nm-class fabrication (Wikipedia/SMEE · F5). As of 2025, CSIS assessed that SMEE produces only i-line and some DUV tools, holds the largest share of i-line equipment, but commands only about 4 percent of the global lithography market, which remains dominated by ASML and Nikon (CSIS · F273). The SSA600 entered mass production at 90nm; a 28nm-class SSA800-10W immersion scanner reportedly completed initial development (reported by Bloomberg in December 2023) but remains in test production and certification, not volume manufacturing (Wikipedia/SMEE · F8, TrendForce · F301). SMEE was placed on the US BIS Entity List in December 2022, which is why the SSA800 had to be designed around US-origin IP (Wikipedia/SMEE · F13). A late-2023 claim by shareholder Zhangjiang Group that SMEE had developed a 28nm machine was later retracted, fueling much of the skepticism about its readiness (TrendForce · F301). A June 2026 AI Futures Project assessment is harsher still: it finds no evidence SMEE has ever produced commercial DUV-immersion tools — or even shipped dry ArF tools — and concludes the SSA800 28nm immersion scanner “appears to exist mostly in statements and industry rumors,” with SMEE still struggling to scale even 90nm front-end and having spun out its only viable business (back-end/packaging litho) to AMIES in 2025 (AI Futures Project · F1090). A December 2025 SMEE government order (model SSC800/10, ~110 million yuan) briefly revived 28nm rumors, but TrendForce reads it as a less-advanced KrF (248nm) system, not the 28nm-class ArF-immersion tool (AI Futures Project · F1090). Treat the January 2026 syndicated claims that the SSA800 had reached “full-scale production” and that China hit 35 percent equipment self-sufficiency as low-credibility: they appear only on press-release aggregators and directly contradict the AI Futures finding (smdailypress/TokenRing · F1167). One real component step: SMEE’s primary light-source supplier RSLaser (科益虹源) reportedly delivered a first domestic 40W 4kHz ArF source — among the hardest 193nm-immersion subsystems — though true immersion productivity needs the 90-120W class ASML/Cymer run, and an indigenous source alone does not establish a working domestic immersion scanner (DigiTimes · F1153).
A scanner needs a dual-stage — a system that exposes one wafer while measuring the next — and here the failure is documented in a primary filing. Huazhuo Jingke’s STAR-board IPO prospectus disclosed that it shipped one lithography dual-stage to SMEE in April 2020 that did not pass acceptance, and that dual-stage sales volume was zero from 2017 to September 2020 (Huazhuo IPO · F441). Its dry dual-stage (priced around 20 million RMB) was usable only at 65nm and above; the immersion dual-stage needed for 45nm and below (priced around 60 million RMB) remained in R&D (Huazhuo IPO · F447). The company — once dubbed China’s “lithography first stock” — terminated its IPO on 26 June 2024, after regulators forced the deletion of the “lithography machine” concept and of language claiming its dual-stage reached or approached international levels (Sina Finance · F452).
The newer hope is Shenzhen SiCarrier Technologies (founded 2022, Huawei-linked), reportedly developing tools for 28nm production and aggressively hiring from ASML and Zeiss (CSIS · F280). SiCarrier-linked Yuliangsheng has produced three immersion DUV machines, delivered to three fabs; the 28nm-class tool under trial reportedly resembles ASML’s 2008-era Twinscan NXT:1950i and uses multipatterning to make 7nm — possibly 5nm at lower yields — with TrendForce judging domestic sub-10nm production unlikely before 2030 (TrendForce · F299). The June 2026 AI Futures assessment now rates Yuliangsheng (staffed by ex-Huawei engineers with Shenzhen state backing) as moving faster than SMEE toward a 28nm immersion scanner, with SMIC already testing its machines and mass production possible as early as 2027 — but cautions it can take a year-plus of fine-tuning to reach commercial yields, then years more to jump to 16nm and then 7nm with a significantly redesigned scanner, so domestic sub-10nm fabrication is still not expected before about 2030 (AI Futures Project · F1088). SiCarrier holds a late-2023 patent describing SAQP with DUV and claiming 5nm-class performance, but that is a patent assertion, not demonstrated high-volume manufacturing (TrendForce/patent · F300). Tellingly, 2026 reporting finds SiCarrier testing equipment in Shenzhen aimed squarely at improving DUV multipatterning yield and throughput — and at SEMICON China emphasizing not lithography but ALD, metrology, etch, CVD, PVD and inspection tools — an acknowledgment that SMIC’s 7nm-equivalent node is at or near the practical ceiling of DUV multipatterning, where each extra mask exposure adds defect and overlay-error opportunities and cuts effective scanner output (SemiAnalysis/AEI · F1166). Where resolution requirements are looser, China competes well: SMEE-related AMIES holds about 90 percent of China’s advanced-packaging lithography market and about 35 percent globally (TrendForce · F302).
SMIC does not publicly disclose its advanced nodes, so the public record comes almost entirely from teardowns of Huawei/HiSilicon Kirin chips. The progression runs N+1 through N+3, all built without EUV on DUV multipatterning:
| Chip | Device / date | SMIC node | What teardowns found |
|---|---|---|---|
| Kirin 9000S | Mate 60 Pro, Sep 2023 | N+2 (7nm-class) | First commercial advanced node from a Chinese foundry without EUV; more advanced than 14nm, larger critical dimensions than 5nm; 13-metal-layer BEOL on 300mm wafers (TechInsights · F4, TechInsights · F10) |
| Kirin 9010 | Pura 70, 2024 | N+2 (same node) | Widely assessed as a 9000S redesign (same Hi36A0 base; 9000S = GFCV120, 9010 = GFCV121) to improve yield, not a node advance (iFixit · F18) |
| Kirin 9020 | 2024 | N+2 | Die area grew across generations because SMIC lacked further scaling (TechInsights · F17) |
| Kirin 9030 | Mate 80 series, Nov 2025 | N+3 | TechInsights confirms a DUV multipatterning (up to 4x) scaled extension of N+2, not a true generational leap; fin pitch/CPP largely unchanged, gains from DUV-driven DTCO + BEOL; aggressively scaled metal pitch causes significant yield challenges and the SoC is likely produced at an operating loss, with many dies discarded or downgraded (TechInsights · F1162) |
Two patterns stand out. First, because the node stopped scaling, Huawei grew the Kirin die size by almost 20 percent across generations just to add functionality — a strategy TechInsights warns will hit a practical limit before larger die become uneconomic (TechInsights · F17). Even so, the part sells: the Mate 80 series (Kirin 9030) moved over 1 million units within 18 days of its November 2025 launch (up 115 percent year-on-year), helping Huawei to its highest China smartphone share in five years in Q1-2026, even as the overall China market shipped down 4 percent on memory shortages (Counterpoint · F1161). Second, even with 7nm capacity, SMIC could not supply Huawei’s AI accelerators at volume during 2024-2025: most Ascend 910B/910C parts tested used TSMC dies, and Huawei built a die bank of more than 2.9 million TSMC 7nm dies — acquired via the intermediary Sophgo for roughly 500 million USD — to cover hundreds of thousands of units across 2024-2025 (SemiAnalysis · F130). That a Chinese national champion stockpiled TSMC dies is itself the clearest signal that domestic 7nm output was constrained by both capacity and yield. The inflection comes in 2026: that TSMC die bank is now effectively exhausted, so future Ascend output depends entirely on SMIC wafers, and SMIC plans to roughly double its advanced-node (7nm-and-below) capacity — SemiAnalysis estimates about 45k wafers per month at end-2025 rising to about 60k in 2026 — to feed a targeted ~600k Ascend 910C units in 2026 (roughly double 2025) (techpowerup · F1091, TrendForce · F1142). Huawei’s newest accelerators stay on this node: the Ascend 920 and the Atlas 350 card’s Ascend 950PR are both reported on SMIC’s N+3 (~6nm/5nm-class) process (techpowerup · F1091).
Node names are marketing labels; what matters is transistor density, yield, and cost. SemiAnalysis’s cross-section teardown of the Kirin 9030 measured SMIC N+3 transistor density at 113.4 million transistors per square millimeter (MTr/mm2) — just above TSMC’s N6 at 107.7 — with a minimum first-metal (M0) pitch of 32.5nm (tighter than Intel 18A’s shipping 36nm), a 57nm contacted gate pitch, and a 228nm cell height (SemiAnalysis · F77). On the same density yardstick the node ladder is unambiguous and the ‘5nm’ label misleads: SMIC N+3 at 113.4 MTr/mm² is N6/N7-class, below true 5nm (TSMC N5 ~134) and roughly half TSMC’s leading edge (N3E 167, N3P 224) — one to two full generations behind, at higher cost and lower yield (SemiAnalysis · F77; TSMC 4Q25 · F1258). SMIC achieves the tighter metal pitch with SAQP rather than TSMC’s SADP, which makes it costlier and lower-yielding; on a normalized basis the density runs about 38 percent below Intel 18A’s high-density library, and SemiAnalysis calls the metal-pitch number a cherry-picked metric (SemiAnalysis · F77). The blunt verdict from 2025 teardowns: SMIC cannot yet make a true 5nm-class node without EUV; N+3 sits closer to 7nm/6nm than to 5nm in absolute scaling, and BEOL yield can collapse abruptly once overlay and variability budgets are exceeded (Tom’s Hardware · F78).
The yield and cost gap is where this turns commercially painful. The figures below are third-party estimates — SMIC discloses nothing — so read them as ranges, not precision:
| Metric | Estimate | Source |
|---|---|---|
| SMIC 7nm (N+2/N+3) yield | ~20% (2024, unverified), rising to ~40-50% in 2025; still cited at ~20-40% in 2026 | HuaweiCentral · F138, TrendForce · F1142 |
| Ascend 910C initial yield | 20-30%, vs ~70% needed for commercial viability | TechNews · F366 |
| SMIC 5nm DUV yield | as low as 20% (AEI/2026 pilot runs) to ~33% of TSMC’s (TrendForce/TechNews) | AEI · F100, TechNews · F369, TrendForce · F1142 |
| Cost vs TSMC equivalent | +40-50% (some cite 2-3x); per-wafer price ~50% higher | AEI · F100, EDN · F244, TechNews · F369 |
| Lithography steps, 7nm | ~34 on DUV vs ~9 on EUV | EDN · F244 |
Figure 2 — Locked out of EUV, SMIC prints 7nm with roughly 34
patterning passes on its hardest layers where EUV needs about 9 — every
extra exposure adds cost and another chance for a defect. Source: EDN
· F244.
SMIC reportedly completed a 5nm process in 2025 using DUV with SAQP — four exposures per critical mask layer — but at roughly one-third of TSMC’s yield and about 50 percent higher per-wafer price (TechNews · F369). As of 2026 that 5nm node is in pilot runs at around 20 percent yield, targeting mass production in 2026 for Huawei and Alibaba next-gen AI processors (a Dec-2025 SMIC-Alibaba 5nm AI-inference chip collaboration was reported), all still via DUV plus SAQP with no EUV; the economics remain punishing — 7nm/5nm prices about 40-50 percent above TSMC, yield under one-third of TSMC’s, viable only under Big Fund III subsidy and protected domestic demand (techpowerup · F1091). Taiwanese reporting expects SMIC to make 7nm only in limited volume through at least 2026, with yields still struggling (TechNews · F365); China reportedly aims to boost combined 7nm/5nm output roughly fivefold within two years (SMIC plus a newly advanced Hua Hong targeting several-thousand 7nm wpm by end-2026), though the ramp still hinges on the imported ASML fleet and not-yet-qualified domestic scanners, so the target reads as aspiration more than committed capacity (TrendForce · F1183). SemiAnalysis framed the whole enterprise as printing the same-denomination banknote at several times TSMC’s cost with greater yield risk (Tom’s Hardware · F78): economically unviable in a free market and sustainable only as a state-funded national-security project (EDN · F244). This is the demand-side mirror of the toolchain squeeze: China made up 87.6 percent of SMIC’s Q4-2025 revenue and 89 percent in Q1-2026 (Americas just 9 percent) as US customers fell away. Wafer counts flatter that picture: SMIC ships ~65% of TSMC’s wafer volume but in 8-inch-equivalents at a ~$930 ASP, where TSMC’s are 12-inch advanced-node — which is why SMIC is only ~7.6% of TSMC by revenue (~$9.3B vs ~$122B) even though the volume gap looks far smaller (SMIC/TrendForce · F828; TSMC 4Q25 · F1258). The squeeze continued even as SMIC’s Q1-2026 revenue reached 2.505 billion USD (+11.5 percent year-on-year) on a 20.1 percent gross margin weighed down by depreciation now running about 44 cents per sales dollar (SMIC FY2025 · F1030, SMIC Q1-2026 · F1046). That margin is the cleanest single proof that node-label parity is not economic parity: SMIC runs its fabs near full utilization yet keeps ~21 cents of gross profit per revenue dollar against TSMC’s ~60 cents (FY2025 gross margin 59.9%) — roughly one-third the profit per wafer dollar (TrendForce/SMIC · F828; TSMC 4Q25 · F1258).
Figure 3 — Same base year, same metric: SMIC’s record $9.327B is
~7.6% of TSMC’s $122.42B — TSMC is ~13x larger. China’s foundry champion
is a small fraction of the global leader even after record growth. TrendForce/SMIC
· F828; TSMC
4Q25 report · F1258.
Even if China stabilizes DUV-based 7nm and 5nm, the leading edge is moving to gate-all-around (GAA) transistors and 2nm-class nodes that lean even harder on EUV — a second wall behind the first. China’s answer is a reported 43 billion USD investment in domestic EUV, pursuing alternative light sources (CSIS · F280). A Huawei/SMEE effort using a laser-induced discharge plasma (LDP) 13.5nm source was reportedly scheduled for trial production around mid-2025, with manufacturing targeted for 2026, but the claims rest largely on unverified social-media photos — one widely circulated image turned out to be an EUV objective-lens alignment interferometer, not a scanner (DigiTimes/GlobalSMT · F260). By late-2025/2026 reporting, a government-run, Huawei-linked Shenzhen effort had assembled a full-scale EUV prototype — reportedly built by analyzing and replicating ASML technology with some components from older machines plus Canon/Nikon parts, occupying an entire factory floor — that can produce some EUV light but remains far from making working chips, with Huawei acting as systems integrator; Beijing targets functional chip production by 2028, while analysts call ~2030 more realistic and commercial scale late-2030s (Asia Times · F1107). The hard wall is the source: the Chinese LDP source produces only about 50-100W versus the at-least-250W required for high-volume EUV (ASML’s LPP sources demonstrate 600W-class), leaving the prototype throughput-limited to roughly 10 wafers per hour, with a follow-up “Hyperion-2” claimed to target ~150W and commercial throughput in 2026; remaining bottlenecks are multilayer mirrors, EUV mask blanks and photoresists, and Chinese-language claims of 250 wafers/hour surpassing ASML come from low-credibility aggregators and should be treated as hype (GlobalSMT · F1123). A more exotic bet is Tsinghua’s steady-state micro-bunching (SSMB), a storage-ring EUV light source whose proof of principle succeeded in Berlin in August 2019 and was published in Nature in February 2021 (Tsinghua · F332); Tsinghua began building a dedicated SSMB test facility in Xiongan in early 2025, aiming at a single accelerator feeding several lithography stations with theoretical continuous power above 1kW and a reach toward 2nm-and-beyond — but the project leader concedes it is “a long road” and currently a light-source alternative, not a usable lithography system, assessed as the most radical leapfrog and least mature path (Tom’s Hardware · F1124). China’s maskless e-beam machine “Xizhi,” announced in 2025 with claims of 0.6nm precision, is too slow for volume production and confined to niche roles such as photomask-making, per CSIS (CSIS · F272).
Sober base-rate forecasting puts indigenous EUV far out. A June 2026 AI Futures Project forecast anchors large-scale commercial 7nm-capable domestic immersion DUV to the early-to-mid-2030s (industry-level 2032-2038, product-level 2033-2036, clustering around 2035) and commercial-scale 5nm-capable EUV to the late 2030s (industry-level 2038-2044, product-level 2037-2039, stretching toward 2040), using ASML’s own roughly 13-year gap from pre-commercial EUV (2006) to volume production (2019) as the reference; it explicitly pushes back on shorter timelines, noting SemiAnalysis’s Dylan Patel predicted fully indigenized DUV and pre-commercial EUV by 2030 (March 2026), but “pre-commercial” is vague, and ASML’s CEO put China 10-15 years behind (AI Futures Project · F1105). CSIS adds a crucial caveat for reading any Chinese announcement: within the central-local system, positive news is currency for funding and recognition, so progress is routinely exaggerated. CSIS concludes that recent claims reveal “more exaggeration than transformation,” and notes that claims of indigenous 5nm capability have circulated for years and been disproven (CSIS · F281). China’s own Made in China 2025 targets — domestic immersion DUV before 2025, domestic EUV before 2030 — illustrate the gap: the immersion-DUV target was effectively missed, with only pre-volume domestic tools existing as of 2025-2026 (CSIS · F308).
China’s answer to Nvidia is not one chip but a crowded field of roughly a dozen accelerator designers, anchored by Huawei’s Ascend line and flanked by a wave of newly public GPU start-ups. The strategy is plain. Where domestic silicon cannot match Nvidia per chip, China wires many chips together and spends extra power and money to close the gap at the system level. The Huawei CloudMatrix 384 — 384 Ascend 910C chips that out-compute an Nvidia rack while drawing about four times the power — is the clearest expression of this energy-for-silicon trade. But an awkward fact sits beneath the 2024–2025 ramp: the most advanced Ascend chips were built on illicitly obtained TSMC dies, that stockpile is now exhausted, and future output is capped not by demand but by supply — specifically by high-bandwidth memory (HBM), the stacked DRAM that feeds an accelerator, which D3 covers in detail. By mid-2026 the next phase is visibly under way: Huawei’s Ascend 950PR entered mass production in April 2026 with Huawei’s own in-house HBM shipping in product form, and all six GPU “little dragons” have completed or cleared their IPOs (TradingView/Reuters · F1051). This document maps the players, benchmarks the chips against Nvidia, sizes the shipment ramp, and surveys the 2025–2026 IPO wave that repriced the sector.
China’s AI-accelerator field splits into three tiers: one dominant incumbent (Huawei), a clutch of merchant GPU and NPU start-ups that mostly listed in 2025–2026, and a set of in-house hyperscaler chip arms (Baidu’s Kunlunxin, Alibaba’s T-Head). The designs diverge on architecture. Some are full-function general-purpose GPUs (GPGPUs) that chase compatibility with Nvidia’s CUDA software; others are domain-specific NPU or TPU designs built only for AI.
| Designer | Flagship part | Architecture / process | Per-chip positioning | Software stack |
|---|---|---|---|---|
| Huawei HiSilicon | Ascend 910C | DaVinci NPU, dual-die, TSMC/SMIC 7nm | ~780 BF16 TFLOPs, ~60% of H100 (SemiAnalysis · F42) | CANN (see D8) |
| Cambricon | Siyuan 590 (MLU590); 690 ramping | NPU, SMIC N+2 7nm, 80GB HBM | 590 ~80% of A100; next-gen 690 H100-class, mass production may slip to H2-2026 (Tom’s Hardware · F1182) | NeuWare / BANG |
| Biren | BR100 | GPGPU “壁立仞”, TSMC 7nm CoWoS | claimed INT8 2048 TOPS, H100-rivalling at 2022 launch (Biren prospectus · F478) | CUDA-compatible |
| Moore Threads | MTT S5000 (Pinghu 4th-gen) | MUSA GPGPU, SMIC-fabbed | H100-class training claims, runs DeepSeek V4 natively (~4,000 tok/s prefill); S4000 was ~A100-class (SCMP · F1181) | MUSA / MUSIFY |
| MetaX (Muxi) | C600 | 7nm GPGPU, MXMACA stack, HBM3e/FP8 | 144GB HBM3e, FP8, positioned between A100 and H100 / vs H200, mass production 2026; C700 in 2027 (Eastern Herald · F1076) | MXMACA (CUDA-alike) |
| Enflame (Suiyuan) | L600 / S60 | DSA (no graphics pipeline), TSMC N6 | L600 claimed to exceed H20 (Enflame · F148) | TopsRider |
| Iluvatar CoreX | Tiangai 100 | 7nm GPGPU | China’s first mass-produced 7nm general GPU, ~A100 (Wikipedia · F192) | IXUCA |
| Kunlunxin (Baidu) | P800 / M100 (2026) | XPU-P, 3rd-gen | P800 ~345 TFLOPS FP16, ~A100/910B-class; M100 (MoE inference, CUDA-compat) launching early 2026, M300 training in 2027 (TrendForce · F1086) | PaddlePaddle / CUDA-compatible |
| Sophgo (Suanneng) | SC11-FP300 (BM1690) | TPU, PCIe, 256GB LPDDR5X, FP8 | datacenter inference, DeepSeek-R1-671B validated (Machine Yearning · F791) | TPU-MLIR |
| Hygon (Haiguang) | DCU K100-AI | GPGPU on AMD-derived IP, 64GB | targets A100 cluster market (Sina Finance · F545) | DTK (ROCm fork) |
Two design philosophies stand out. Moore Threads, MetaX, Biren and Iluvatar build full-function GPGPUs and chase low-friction CUDA migration; Moore Threads was founded by Nvidia’s former China head, Zhang Jianzhong, and MetaX by an ex-AMD GPU design lead, which frames them as the “China Nvidia” and “China AMD” (STCN · F561). Enflame instead uses a domain-specific architecture (DSA) tuned purely for AI with no graphics pipeline, which groups it with Huawei’s Ascend NPU, Google’s TPU and Cambricon (Sohu · F389). Sophgo descends from Bitmain’s crypto-mining ASIC heritage — it was spun out of Bitmain in 2019 under co-founder Micree Zhan — and that lineage informs both its energy-efficiency focus and, as the next section shows, its role as the conduit for Huawei’s TSMC-die scheme (Machine Yearning · F789; Jon Peddie Research · F844).
The single most important fact about the Ascend 910C overturns the assumption that it was a triumph of SMIC’s domestic 7nm process. TechInsights teardowns of multiple samples — including chips acquired by the US government — found the compute dies were fabricated on TSMC’s 7nm process, not SMIC’s (TechInsights · F15). US authorities determined that Huawei acquired roughly 2.9 million TSMC 7nm dies routed through Sophgo, a Cayman-registered design firm described as a Bitmain affiliate, in a sanctions-evasion scheme. TSMC was reportedly fined about USD1 billion, cut ties with Sophgo, and reiterated that it had made no direct Huawei supply since September 2020 (Tom’s Hardware · F225).
That stockpile of more than 2.9 million dies is what actually sustained the 2024–2025 Ascend ramp. SemiAnalysis estimates it was enough for roughly 800,000 Ascend 910B and 1.05 million 910C across the two years, and every 910B and 910C teardown by the US government and TechInsights used TSMC dies, not SMIC (SemiAnalysis · F811). The 910C is a dual-chiplet package — effectively two 910B-class DaVinci dies — combining 32 cores, ~256 TFLOPS FP16, 84MB of on-chip SRAM, and four HBM2 channels, plus 16 Arm-compatible Taishan CPU cores for host-free operation, joined by a CoWoS-S-style silicon interposer (TechInsights · F224; TechInsights · F190). The memory was stockpiled foreign silicon too: teardowns found older HBM2E from Samsung and SK Hynix, believed procured before Washington’s 2024 expansion of advanced-memory restrictions (TechInsights · F191).
The decisive shift is that, as of early 2026, the TSMC die bank is exhausted (SemiAnalysis · F811). Future Ascend output now depends entirely on SMIC N+2 (7nm-class DUV) wafers plus domestic CXMT HBM and domestic packaging, removing the smuggled-die cushion. SMIC’s 910C yield reportedly improved from ~20% in 2024 to nearly 40% in 2025, making the production line profitable for the first time, with SMIC targeting 60% to match TSMC’s H100-class economics; the Financial Times, DigiTimes and Reuters corroborate the 20-to-40% trajectory independently (FT/DigiTimes · F770). Advanced packaging is a further constraint: SemiAnalysis estimates only ~75% of chips survive the packaging step (TechInsights/SemiAnalysis · F190).
The backstop for that domestic supply chain is, reportedly, hidden in plain sight: a clandestine manufacturing network. Per DigiTimes and DSET research, Huawei is widely believed to run a de-facto IDM of roughly 11 fabs across seven nominally-independent entities — none publicly linked to Huawei — with at least five reportedly sub-7nm capable, the Shenzhen core (Pensun, PXW, SwaySure, Pengjin) wholly owned by the Shenzhen-SASAC state vehicle SZMII and run behind the scenes as a single IDM spanning logic, foundry and memory (DigiTimes/DSET · F762; DigiTimes/FT · F981). The SiCarrier tool arm was spun out of a Huawei lab, and SwaySure — led by the late ex-Elpida president Yukio Sakamoto — supplies Huawei DRAM and is researching HBM stacking, signaling a deliberate transfer of Japanese memory know-how (DSET · F776). The network is the manufacturing answer to the exact gap above: it aims to internalize the tool, wafer and packaging steps that the exhausted TSMC die bank and HBM controls otherwise gate, while SMIC channels ~26,000 of its ~50,000 wpm advanced-node capacity to Ascend dies (SemiAnalysis · F980).
Figure 1 — The manufacturing backstop for Ascend once the
smuggled-die cushion is gone: ~11 fabs across 7 entities, none publicly
tied to Huawei, ≥5 sub-7nm capable, run as one de-facto IDM under the
Shenzhen-SASAC vehicle SZMII (reportorial, per DigiTimes/DSET/FT — not
officially confirmed). Source: DigiTimes/DSET
· F762; SZMII
quartet · F981; SwaySure
DRAM · F776; PXW/PST
· F777; FN5
orphans · F206; SMIC
26k/50k wpm · F980.
On a per-chip basis, the 910C is roughly a generation behind. A single 910C delivers ~780 BF16 TFLOPs — about one-third of an Nvidia GB200 chip (~2,500 TFLOPs) and roughly 60% of an H100. All three figures are dense BF16 with sparsity off, the only apples-to-apples basis: on that convention the 910C’s ~780 TFLOPs is ~60% of an H100’s ~990 and ~1/3 of a GB200’s ~2,500 — yet the 910C carries more HBM than an H100 (128GB vs 80GB), which is why brute-force scale-out can close the system gap even when the per-chip gap cannot (SemiAnalysis · F42).
| Metric | Ascend 910C | Nvidia H100 | Nvidia GB200 (per chip) |
|---|---|---|---|
| BF16 dense compute | ~780 TFLOPs | (910C ≈ 60% of H100) | ~2,500 TFLOPs |
| Relative per-chip | ~1.0x | ~1.7x of 910C | ~3.2x of 910C |
| Memory | 8 stacks HBM2E, ~3.2 TB/s | HBM3 | HBM3E |
| Process | TSMC/SMIC 7nm | TSMC 4N | TSMC 4NP |
Source: per-chip figures from SemiAnalysis · F42; Chinese trade analysis describes the dual-die 910C as combining two 910B dies with ~800 TFLOP/s FP16 peak and ~3.2 TB/s memory bandwidth (Tencent News · F438). This per-chip deficit is the entire reason China leans on scale-out.
Huawei’s answer to the per-chip gap is the CloudMatrix 384 (CM384), officially the Atlas 900 A3 SuperPoD: 384 Ascend 910C NPUs and 192 Kunpeng CPUs across 16 cabinets, launched in March 2025. It delivers ~300 PFLOPs of dense BF16 compute — about 1.7x an Nvidia GB200 NVL72 — by using five times as many chips, each at roughly one-third the performance (SemiAnalysis · F43). At the system level it also leads on memory: ~49.2 TB of aggregate HBM and 1,229 TB/s of bandwidth, roughly 3.6x the HBM capacity and 2.1x the bandwidth of the GB200 NVL72’s 13.8 TB and 576 TB/s — a genuine edge for large-model inference (SemiAnalysis · F44).
The trade is power and money. The CM384 draws ~560 kW against ~145 kW for a GB200 NVL72 — 4.1x the power and 2.5x worse power per FLOP — and reportedly costs ~USD8 million, nearly 3x a GB200 NVL72 (SemiAnalysis · F45). This is a deliberate energy-for-silicon trade that China, with abundant power, can afford. The interconnect makes the brute-force approach work. Each 910C carries seven 400G optical modules, and the supernode uses 6,912 400G transceivers to deliver 2.8 Tbps inter-card bandwidth at sub-microsecond latency in a non-blocking all-to-all topology, with the UnifiedBus (UB) plane giving each chip 392 GB/s of unidirectional bandwidth (EET-China · F412). Huawei goes all-optical for scale-up where Nvidia stays on copper, drawing on 30 years of optical-communications IP and reportedly cutting optics power and cost by more than 30% with DSP-free linear-pluggable modules (Tencent News · F418).
| System | Chips | Dense BF16 | HBM capacity | Memory BW | Power |
|---|---|---|---|---|---|
| Huawei CM384 | 384x 910C | ~300 PFLOPs | 49.2 TB | 1,229 TB/s | ~560 kW |
| Nvidia GB200 NVL72 | 72x Blackwell | ~180 PFLOPs | 13.8 TB | 576 TB/s | ~145 kW |
| Ratio (CM384 / NVL72) | 5.3x | ~1.7x | ~3.6x | ~2.1x | ~4.1x |
All cells from SemiAnalysis · F43, · F44, · F45.
Figure 2 — Behind per chip, ahead per system: the 910C trails Nvidia
silicon ~3x per chip, but CloudMatrix 384 out-computes a GB200 NVL72 by
~1.7x — at 4.1x the power draw. Source: SemiAnalysis
· F43.
The successor Atlas 950 SuperPoD, unveiled at Huawei Connect in September 2025, scales to 8,192 next-gen Ascend 950DT chips delivering 8 FP8 ExaFLOPs across 160 cabinets, with SuperClusters reaching beyond 500,000 NPUs (Huawei · F632). Huawei gave it its first global debut at MWC Barcelona in March 2026, detailing 16 PB/s of total interconnect bandwidth over the all-optical UnifiedBus, 160 cabinets (128 compute + 32 comms) across ~1,000 m², a claimed 95% compute efficiency on the 8,192-NPU pod, and 56.8x more NPUs than Nvidia’s NVL144 has GPUs — the explicit scale-out-to-beat-per-chip-deficit pitch against Nvidia and AMD’s MegaPod, with commercial rollout planned for Q4-2026 (Huawei/TechRadar · F1102). The 950DT that anchors it uses Huawei’s higher-grade in-house HiZQ 2.0 (~HBM3-class, 144GB, 4 TB/s) memory and is slated for Q4-2026 (Tom’s Hardware · F1156). At MWC Huawei also delivered on its 2025 pledge to open-source the CANN compute architecture (operator/acceleration libraries, graph engines, languages) and published the UnifiedBus 2.0 spec; CANN 8.0 now supports PyTorch, vLLM, SGLang, Triton and TileLang, broadening the framework on-ramp even as Huawei concedes the developer experience still trails CUDA (Huawei · F1101). The serving software that turns this hardware into a system-level moat — Prefill-Decode-Caching disaggregation over the UB plane — is covered in D8.
Huawei shipped 507,000 Ascend units in 2024 (mostly 910B) and 805,000 in 2025, of which 653,000 were the more advanced 910C (SemiAnalysis · F31). The 2025 figure is unusually well corroborated. SemiAnalysis’s supply-side die-bank model (~805,000 units) and IDC’s demand-side channel tracker (~812,000 Huawei AI chips, via Reuters) agree within ~1% despite opposite methodologies, and both sit above Mizuho’s earlier estimate of more than 700,000 (Reuters/SemiAnalysis · F977). The residual uncertainty is in the mix (the 910B-versus-910C split) and in whether “units” mean finished accelerators or dies, not in the ~800,000 headline.
| Year | Total Ascend units | Of which 910C | Source |
|---|---|---|---|
| 2024 | 507,000 (mostly 910B) | — | SemiAnalysis · F31 |
| 2025 | ~805,000 / ~812,000 | 653,000 | SemiAnalysis/IDC · F977 |
| 2026 (910C plan) | ~600,000 | 600,000 | SemiAnalysis · F790 |
| 2026 (950PR target) | ~750,000 | — | TradingView/Reuters · F1051 |
| 2026 (total Ascend dies) | ~1.6M | (incl ~600k 910C) | TradingView/Reuters · F1051 |
For 2026, Huawei targets ~600,000 910C units and ~750,000 of the new Ascend 950PR — out of a total Ascend family of roughly 1.6 million dies — though the 950PR figure is still expected to lag demand under US tool curbs (TradingView/Reuters · F1051). The 950PR is no longer a roadmap promise: after engineering samples reached hyperscalers in January 2026 and the product debuted at Huawei’s 20 March China Partner Conference, mass production began in April 2026, with full-scale shipments expected H2-2026 (TradingView/Reuters · F1051). It ships in two memory configurations — a DDR-memory variant at ~RMB50,000 (~USD6,900)/card and a premium HBM variant at ~RMB70,000 using Huawei’s own HiBL 1.0 (~HBM2e-class, 128GB, 1.6 TB/s) — a deliberate split that reserves scarce in-house HBM for the premium SKU while DDR parts serve capacity-bound inference, de-risking the ramp from CXMT HBM3 uncertainty (Tom’s Hardware · F1156). Huawei has guided to roughly USD12 billion in AI-chip revenue for 2026 as Nvidia’s China share craters toward zero (SemiAnalysis · F790).
Figure 3 — The shipment ramp’s defining tension in one frame: a
clean +58.8% YoY arc to 805k (2025), then a 2026 fork — the ~1.35M
stated target (600k 910C + 750k 950PR) runs 4–5x ahead of the ~250–300k
that domestic CXMT HBM can actually feed. Demand is set by policy;
supply is gated by memory. Source: SemiAnalysis
· F31, ·
F178; 2026
target/revenue · F790; HBM-gated
ceiling · F668; derived
CAGRs · F1293.
Figure 4 — China’s flagship accelerator vendor is a rounding error
at global scale: Huawei’s ~$12B 2026 Ascend target is ~1/16 of Nvidia’s
$193.7B FY2026 Data Center revenue and below a single Nvidia DC quarter
($62.3B). Capacity
· F879; Nvidia
· F1256.
The 950PR is also gaining the demand the 910C lacked: where Huawei struggled to push the 910C into private firms, ByteDance and Alibaba plan to order the 950PR (Reuters/CNBC · F193), and ByteDance alone has committed to spend more than USD5.6 billion on Ascend chips in 2026, up from near zero; Huawei reportedly raised the 950PR price ~20% on demand strength after DeepSeek’s V4 launch (TradingView/Reuters · F1051). The 950PR roadmap claims ~2.87x H20 compute at FP4 (TrendForce · F810); the training/decode-focused 950DT follows in Q4-2026 (Tom’s Hardware · F1156).
Across the whole domestic field, IDC data (via Reuters) puts 2025 China AI-accelerator shipments at ~4 million cards. Domestic vendors took ~1.65 million — 41%, breaking 40% for the first time — while Nvidia held ~2.2 million (~55%, down from ~95% before the controls). The switch the controls were meant to prevent is now self-reinforcing: the export-compliant H20 Nvidia was allowed to sell China (~148 FP16 TFLOPs) is out-computed roughly 5x by China’s own 910C (~780 TFLOPs), so by 2026 the controlled Nvidia option was weaker than the domestic one (Asia Times · F71; SemiAnalysis · F42). Within the domestic camp, Huawei Ascend dominates (~812,000, ~20% of the total addressable market), followed by Alibaba’s T-Head at 265,000, Kunlunxin and Cambricon at ~116,000 each, and Hygon, MetaX and Iluvatar in the low single-digit percentages (IDC/Reuters · F745). One caveat: this 41% volume share overstates value share, because Nvidia parts carry far higher average selling prices than domestic 7nm cards, so 41% volume self-sufficiency does not mean 41% of China’s AI-compute spend is domestic (IDC · F1016).
Figure 5 — Real localization momentum (8%→41% in three years; Huawei
~812k of ~1.65M domestic cards), but the split is by unit volume —
Nvidia parts carry far higher ASPs, so by value its lead is wider than
55/41 implies. IDC/Reuters
via the-decoder · F745; unit-vs-value
caveat · F1016.
Figure 6 — The four-point view of the same crossover: domestic share
climbs 8%→30%→~41% (units) against Nvidia’s
92%→70%→~55% through the 2024–25 export-control/DeepSeek
inflection, with Bernstein projecting ~55% domestic by 2027. Axis is
unit volume — Nvidia’s value share stays higher on far larger ASPs.
Source: IDC · F1283;
2024
1.9M/2.7M, IDC via Enflame prospectus · F384; 2025
1.65M/4M, IDC via Reuters · F745; 2027E
Bernstein · F957; unit-vs-value
caveat · F1016.
Cambricon shows the same surge as a merchant supplier. Full-year 2025 revenue reached RMB6.497 billion (+453% year on year) with RMB2.059 billion in net profit — its first annual profit in five years as a listed company. Sized against the global leader, even the breakout domestic winner is a sliver: Cambricon’s Q1-2026 revenue of ~RMB2.88B (~$423M, +160% YoY) is about 1% of Nvidia’s $39.1B Q1-FY2026 Data Center quarter — separating stock-market enthusiasm from revenue reality (Tom’s Hardware · F1045; Nvidia · F1256). The profit was driven by the mass ramp of the MLU590 and a single dominant customer, ByteDance, at 79% of Q1–Q3 revenue (Cambricon filing · F361; Cambricon filing · F356). The momentum carried into 2026: Q1-2026 revenue hit RMB2.885 billion (+159.56% year on year) with RMB1.013 billion net profit (+185%), an above-54% gross margin, and operating cash flow turning positive at +RMB834 million — a single quarter that roughly matched all of H1-2025 revenue, sending the stock to its +20% daily limit at RMB1,700 on 30 April 2026 and a market cap above RMB710 billion (~250–348x trailing earnings) (Tom’s Hardware · F1045). It targets ~500,000 accelerators in 2026, roughly triple 2025 output — including as many as 300,000 of the advanced Siyuan 590 and next-gen Siyuan 690 (H100-class), the latter possibly slipping to H2-2026 — though SMIC 7nm yields reported around 20% and limited HBM threaten the target (Bloomberg/Tom’s Hardware · F1182). A structural tailwind underpins both Cambricon and Huawei: as of Q1-2026 they are the only two firms on China’s government-approved AI-hardware procurement list, with Nvidia excluded even after the H200 easing — the policy mechanism channeling state and SOE buyers to the two approved vendors (Yahoo Finance · F1199).
The clearest signal of how China repriced this sector is the listing frenzy of late 2025 and early 2026. Frost & Sullivan data cited in the prospectuses projects China’s AI-chip market growing from ~RMB142.5 billion in 2024 to ~RMB1.34 trillion in 2029, a ~54% compound annual growth rate, which framed the surge (STCN · F561).
| Company | Listing | Date | Raise | First-day move / valuation |
|---|---|---|---|---|
| Moore Threads | STAR (Shanghai) | 5 Dec 2025 | ~RMB8B (~USD1.13B) | +425% to ~RMB282B mkt cap (Bloomberg · F237) |
| MetaX (Muxi) | STAR (Shanghai) | 17 Dec 2025 | ~RMB4.2B | +693% to ~RMB332B (~USD42B) (Global Times · F151) |
| Biren | HKEX (6082) | 2 Jan 2026 | ~HKD5.58B (~USD717M) | +76% close, ~HKD82.8B day-one mkt cap; HK’s first 2026 listing, largest Chapter 18C ever (Fortune · F1062) |
| Iluvatar CoreX | HKEX (9903) | 8 Jan 2026 | ~HKD3.7B (~USD474M) | +31.5% open, ~USD5.3B debut val, ~414x oversubscribed (Caixin · F1063) |
| Enflame | STAR (Shanghai) | cleared SSE 15 Jun 2026 | ~RMB6B (~USD888M) | listing expected H2-2026; ~USD2.8B pre-IPO val (Bloomberg · F1087) |
| Kunlunxin (Baidu) | HKEX + STAR (dual) | HK filed Jan 2026; STAR guidance 7 May 2026 | — | HK val mooted ~HKD100B (~USD13B) (TrendForce · F1086) |
These valuations sit on top of deep losses and extreme customer concentration. MetaX posted a 2025 net loss of ~RMB830 million on ~RMB1.6 billion in revenue, yet surged ~693% on day one to ~USD42 billion; both MetaX and Moore Threads had under 5% free float, which amplified the move (Global Times · F151; STCN · F561). Moore Threads carried cumulative losses of ~RMB5.5 billion over 3.5 years, with R&D equal to 626% of cumulative revenue and 98.29% of H1-2025 revenue from its top five customers — mostly telecom operators and state compute centres (Moore Threads filing · F311; · F313). Biren accumulated more than RMB6.3 billion in losses by mid-2025 and held just 0.16% of China’s smart-compute chip market in 2024, the year Nvidia and AMD held 98% of China’s general-GPU market (Biren filing · F473). Enflame depended on Tencent for ~84% of 2025 revenue while losing ~RMB4.3 billion cumulatively (Enflame filing · F381). Iluvatar, the most diversified, cut customer concentration from 94% to 39% of revenue as its customer count rose from 22 to 181 (Iluvatar filing · F509). By mid-2026 the mania had held but compressed off the debut peaks: Moore Threads traded ~RMB669 on 20 June 2026 (vs its RMB114.28 issue price and ~RMB941 high), MetaX grew FY2025 revenue 121.3% to RMB1.6 billion with C-series shipments up 147.3% to 33,600 units yet said it would not break even before 2026 at the earliest, and both HK names (Biren, Iluvatar) still traded above offer (Yahoo Finance · F1075; Eastern Herald · F1076). MetaX is now pursuing a Hong Kong H-share secondary listing, with a 29 June 2026 shareholder vote on an offering of up to 5% of enlarged capital (Eastern Herald · F1076). The market is pricing a forward domestic-substitution narrative, not current fundamentals.
One structural fact frames everything above: China’s AI-accelerator output is limited by supply, not demand. Demand is enormous and policy-amplified. Alibaba alone committed at least RMB380 billion (~USD53 billion) over three years to cloud and AI infrastructure, and ByteDance is spending ~RMB160 billion in 2025 — more than Baidu, Alibaba and Tencent spent combined in 2024 (Alibaba · F721; Silicon · F725). Policy pulls that demand toward domestic silicon: an August-2025 rule required state data centres to source at least 50% of chips locally; by November 2025, state-funded builds were barred from foreign accelerators entirely; and the NDRC is reportedly drafting a five-year ~USD295 billion national compute grid mandating ≥80% domestic technology (TechTimes · F761). The Cyberspace Administration directly ordered Alibaba and ByteDance to stop buying Nvidia’s China-spec chips (Sina · F567). The January-2026 thaw that allowed Nvidia H200 (and AMD MI325X) exports to China on a case-by-case basis did not reverse this: Chinese firms ordered 2 million-plus H200s and ~10 firms were cleared, yet by May 2026 not a single H200 had been delivered — the US State Department stalled shipments on security review while Beijing steered firms back to domestic parts, so the formal easing left the domestic-accelerator demand pull intact (CNBC · F1128).
The binding constraint is HBM, not logic. SMIC’s advanced-node capacity — ~45,000 wafers a month at the end of 2025, rising to 60,000 in 2026 — can produce die for over 1 million Ascend chips a year using only ~20,000 wafers a month, so logic capacity is not the limit (SemiAnalysis · F829). HBM is. SemiAnalysis estimates CXMT can make only ~2 million HBM stacks in 2026, enough for just 250,000–300,000 Ascend 910C packages (each using 8 stacks); if HBM were abundant, 2026 Ascend output would rise from ~300,000 to more than 5 million units, an order-of-magnitude cut imposed by HBM scarcity (SemiAnalysis · F668). That CXMT ~2-million-stack figure traces to a single source and carries wide error bars — plausibly 1–4 million finished stacks — and much of it is lower-grade HBM2 or HBM2E rather than leading-edge HBM3E, a quality gap the unit count hides (SemiAnalysis · F878; · F1011). The full HBM picture — CXMT’s capability and grade, and the TSV/stacking-tool chokepoint — is the subject of D3.
China’s memory industry tells two different stories. In commodity memory — the 3D NAND flash that stores data and the DRAM that holds it for active use — Chinese firms have closed most of the gap to the global leaders: YMTC’s latest NAND now matches SK Hynix on bit density (TechInsights · F11), and CXMT’s DDR5 sits roughly four years behind the front line (ChinaTalk · F55). In high-bandwidth memory (HBM) — the stacked DRAM bolted to every AI accelerator — China is still about three generations behind (ChinaTalk · F66), and a December 2024 US export rule turned that lag into a hard ceiling on the country’s AI compute. China has shown it can build advanced memory. But HBM — not logic — now caps how many AI chips it can actually assemble, and that is exactly where the next wave of state investment is heading. The 2026 memory super-cycle has supercharged the commodity side: CXMT posted FY2025 revenue of RMB 61.8B (+155.6% YoY) and a Q1-2026 quarter of RMB 50.8B (+719% YoY, net profit RMB 33B), cleared its STAR Market IPO review on 27 May 2026, and won CSRC registration approval on 15 June 2026 for a ~RMB 29.5B (~$4.2-4.35B) raise — the largest A-share IPO of 2026 (SSE/Global Times · F1037; SCIO · F1038).
3D NAND flash stores bits in vertical stacks of memory cells. More layers per stack means more bits per square millimeter of silicon, and that density is the metric that drives cost competitiveness. For years YMTC (Yangtze Memory Technologies) trailed Samsung, SK Hynix, Kioxia and Micron on it. That gap has now effectively closed.
In early 2025, TechInsights tore down a ZhiTai TiPro9000 SSD and found YMTC’s fifth-generation 3D TLC NAND, built on its Xtacking 4.0 architecture and carrying 294 total layers (232 physically active layers) — the highest total vertical layer count of any commercial NAND at the time (TechInsights · F2). The 294 figure is an equivalent-density number: YMTC reaches it by string-stacking two decks of 232 physical TLC layers and bonding them, at an interface speed of 3,600 MT/s (Sina Finance · F442).
The resulting bit density is what matters for cost. TechInsights measured YMTC’s fifth-generation TLC at more than 20 Gb/mm², roughly matching SK Hynix’s G9 3D TLC and only slightly below Kioxia/SanDisk’s BiCS8 3D QLC at 22.9 Gb/mm² (TechInsights · F11). YMTC has closed the density gap with the non-sanctioned leaders. It is not the outright technology leader — SK Hynix holds the active-layer record at 321 layers, and the leaders collectively span the 200-to-321-layer class — but YMTC now competes on the metric that drives the economics (TechInsights · F242).
| Maker | Layer count (class) | Bit density | Source |
|---|---|---|---|
| YMTC X4 (Xtacking 4.0) TLC | 294 total / 232 active | >20 Gb/mm² | (TechInsights · F2; TechInsights · F11) |
| SK Hynix G9 TLC | 321 active | ~comparable (>20 Gb/mm²) | (TechInsights · F11; TechInsights · F242) |
| Kioxia/SanDisk BiCS8 QLC | ~218 | 22.9 Gb/mm² | (TechInsights · F11) |
| Samsung V9 | ~290 (286 benchmark) | — | (Sina Finance · F442; DigiTimes · F819) |
YMTC’s roadmap pushes further. Its X5 generation — an X5-9080 2TB 3D TLC part and a 3D QLC X4-6080, both supporting 4,800 MT/s — is penciled for 2026 mass production, and the next architecture is expected to exceed 300 layers and require tri-deck bonding (three 3D NAND structures bonded together) (Sina Finance · F442; DigiTimes · F819). By early 2026 the shipping product remained the 294-layer Xtacking 4.0 TLC, now joined by a 267-layer variant in production; YMTC debuted its first commercial PCIe 5.0 SSD on in-house Xtacking flash, is targeting ~150,000 wafers a month and ~15% of global NAND supply by end-2026, and Xtacking 5.0 — the step expected to match or surpass the 321-layer class — is the next-gen move, not yet launched (TrendForce · F1067).
The market has rewarded that ramp. Counterpoint puts YMTC’s NAND revenue share at ~13% in Q1-2026, up the ladder from 8% in Q1-2025 (9%, 10%, 11% through the year) — now tied for roughly No. 4 globally alongside Micron and SanDisk, behind Samsung (29%), SK Hynix (18%) and Kioxia (14%). Q1-2026 revenue of ~$2.6B (up ~445% YoY) was YMTC’s third straight double-digit-growth quarter, riding domestic demand and a NAND market that hit a record ~$46B in the quarter (3.5x YoY) — putting YMTC ahead of its own end-2026 share trajectory (TechNode · F1116). NAND is the exception that proves the rule: YMTC’s near-frontier ~13% revenue share — won by vertical stacking that sidesteps EUV — sits against China’s ~0% in HBM, marking exactly where China closed the gap and where it remains structurally stuck (Counterpoint via TechNode · F1116; TrendForce NAND · F1269).
The strategic point sits underneath the layer counts: YMTC localizes its tools faster than any other Chinese fab. It reached 45% domestic tool adoption in 2024 — the highest in the country, against roughly 22% at SMIC’s Jingcheng fab and 18% at Lingang (DigiTimes · F801). Its registered third Wuhan fab, founded in September 2025 with RMB 20.72 billion of capital and explicitly targeting 100% domestic equipment, was fast-tracked to H2-2026 mass production, a year ahead of the original plan (Tencent News · F373; DigiTimes · F819). The reason 3D NAND localizes faster than logic is structural: scaling vertically shifts the bottleneck away from lithography — where China is weakest — toward high-aspect-ratio etch, deposition and bonding, where domestic tool makers such as AMEC, NAURA and Piotech are strongest (DigiTimes · F801). That same bonding muscle becomes the bridge to HBM, as Section 4 shows.
DRAM is the working memory of every computer. CXMT (ChangXin Memory Technologies) is China’s leading DRAM maker, and over 2024-2025 it moved from a near-zero global share into volume DDR5 — the current-generation standard for PCs and servers. By revenue the world-#4 label still resolves to a single-digit sliver: CXMT held ~4% of global DRAM revenue in Q2-2025, rising toward ~7-8% by late-2025, against a ~91-95% incumbent oligopoly — China’s #1 DRAM maker is about 1/6 of SK Hynix by DRAM revenue (CXMT IPO/Digitimes · F109; CXMT SSE · F1037).
TechInsights found CXMT’s first commercial DDR5 16Gb die inside a Gloway DDR5-6000 UDIMM, built on the company’s 16nm-class G4 process. The die measures 66.99 mm² with a bit density of 0.239 Gb/mm², and the move to 16nm cut the DRAM cell size 20% versus the prior G3 18nm node (DigiTimes · F53). CXMT skipped the intervening 17nm node to jump straight to 16nm (dram.com.cn · F341).
The capability is real, but so is the gap. TechInsights assesses CXMT’s DDR5 density as comparable only to what the market leaders shipped in 2021, leaving it roughly four years behind Samsung, SK Hynix and Micron (ChinaTalk · F55). Even that four-year reading is an improvement: earlier estimates put the gap at six to eight years (ChinaTalk · F55). TechNews Taiwan, citing TechInsights, frames it as about three years behind Korean and US makers (TechNews · F450). The lag, then, sits somewhere in the three-to-four-year band, depending on which metric you weight.
The gap shows up most clearly in cost. CXMT’s DDR5 die, at roughly 67 mm², is about 40% larger than the comparable Samsung product, so fewer chips come off each wafer and the cost structure stays less favorable until the node gap closes (DigiTimes · F117). This die-size penalty is why CXMT’s ~11% capacity share overstates its competitiveness: a ~40%-larger DDR5 die on a 16nm-class (≈2021-density) process yields ~40% fewer chips per wafer than Samsung’s denser 1b/1c nodes, so the bit-output and cost gap runs wider than the wafer headcount suggests (Digitimes · F109). Two trends are converging to fix that. First, yield. Chinese reporting summarizing Citi and market data says CXMT’s DDR5 average yield broke through 80% in H2 2025, after Citi had earlier forecast a climb from around 40% to 80-90% within a year (dram.com.cn · F341); by early 2026 the ~80% figure (up from ~50% at initial mass production) was confirmed, though NH Investment & Securities cautions DDR5 yields still sit below market expectations and that post-IPO tool orders equivalent to ~30,000-40,000 wafers have sharpened scrutiny of CXMT’s medium-term trajectory (ExportSemi · F1042). Analysts expect full DDR5 yield parity around late 2026 (DigiTimes · F117). Second, the next node. The G5 (15nm-class) process completed development by late 2025, with samples expected in 2026 and realistic mass production in late 2026 — achieved without EUV lithography by reusing existing equipment, in the manner of Micron’s 13nm DRAM (DigiTimes · F54; Tom’s Hardware · F850). The remaining hard constraints are US-restricted high-aspect-ratio and low-temperature etch tools, which advanced DRAM nodes still need (DigiTimes · F54).
CXMT’s product breadth is now substantial. At IC China in November 2025 it showed DDR5 in 16Gb and 24Gb densities up to 8,000 MT/s across seven module types, plus LPDDR5X up to 10,667 MT/s, and claimed both lines rank in the industry’s “first tier” (CXMT · F320; Tom’s Hardware · F850). Its capacity is large. 12-inch fabs across Hefei and Beijing give it the biggest DRAM capacity in China and the fourth-largest globally — around 200,000-265,000 wafers a month in 2025, with IPO proceeds funding expansion to 300,000 by end-2026 and beyond 400,000 thereafter; SemiAnalysis is more bullish still, modeling ~350,000-420,000 WSPM at end-2026 (~17% of global DRAM, up from ~13% in 2025) and a position near No. 3 by wafer capacity, just behind Micron (dram.com.cn · F364; SemiAnalysis · F1040). The IPO’s ~RMB 29.5B is earmarked RMB 13B for a Phase-II fab, RMB 7.5B for line upgrades and RMB 9B for next-gen DRAM R&D (SCIO · F1038). Global DRAM share grew from near-zero in 2020 to about 5% by 2024 (TechNews · F450), reaching ~7.67% by the time of the IPO filing (SSE/Global Times · F1037). For incumbents, the worry is straightforward: once CXMT reaches yield parity in late 2026, it can price aggressively in the low-to-mid PC, phone and appliance segments (DigiTimes · F117) — and as the big-3 reallocate toward HBM and DDR5 and ramp down legacy DDR4, CXMT (and YMTC for NAND) are stepping in as the marginal swing supplier into H2-2026, with analysts flagging that a state-backed maker able to run at a strategic loss could oversupply specific DDR5 segments and trigger a price correction (Tom’s Hardware · F1061). For now the cycle runs the other way: TrendForce’s May-2026 survey had conventional DRAM contract prices up a record ~90-95% QoQ in Q1-2026 and a projected +58-63% in Q2, with NAND +70-75% in Q2 (the first time this cycle NAND outpaced DRAM) — driven by AI capacity reallocation and HBM crowding out commodity DRAM (Micron cites a ~3:1 HBM-to-DDR5 wafer conversion), and a shortage TrendForce expects to persist through 2026 (TrendForce/Tom’s Hardware · F1054).
Figure 1 — CXMT’s percentages are huge but off a small base: ~$8.6B
total revenue is ~1/8 of SK Hynix (~$68B) and ~7% of the ~$125B
big-three DRAM pool. The super-cycle lifts everyone; the leaders bank
far more. CXMT
IPO/SSE · F1037; TrendForce
big-three DRAM · F1259.
Figure 2 — CXMT’s capacity is the catch-up curve underneath the
whole dive: DRAM wafer capacity rose more than 10x in five years (~20k
wafers/month in 2020 to ~270-280k in 2025, ~15% of global DRAM output),
with a ~300k+ 2026 target, while its within-2025 DRAM unit share climbed
~6% (Q1) to ~8% (Q4, rank #4) on FY2025 revenue of RMB61.8B (+155.6%
YoY). This commodity-DRAM scale is what makes the HBM cliff (Figure 5)
the binding limit rather than DRAM capacity. Source: DigiTimes/TechNews
· F406; stcn
institutional est. · F481; CXMT
IPO/SSE · F1037.
HBM stacks multiple DRAM dies vertically and connects them to a logic die with thousands of through-silicon vias, delivering the memory bandwidth an AI accelerator needs. It is the hardest memory product to make, and it is where China’s lag is widest. The scale of the shut-out is the point: HBM is a ~$54.6B market in 2026 of which China earns ~0%, while the three non-Chinese incumbents — SK Hynix ~58%, Samsung ~21%, Micron ~21% — own essentially all of it (BofA via SK Hynix · F1266; Counterpoint shares · F215).
Figure 3 — HBM is the memory that makes AI accelerators work, and
China earns ~0% of a ~$54.6B (2026) market the three non-Chinese
incumbents — SK Hynix ~58%, Samsung ~21%, Micron ~21% — own almost
entirely. The binding constraint on China’s AI-compute ambition. BofA
via SK Hynix outlook · F1266; Counterpoint
shares · F215.
CXMT began mass-producing HBM2 in the second half of 2024 (ChinaTalk · F66); Reuters and others date the start to around August 2024, in partnership with the OSAT firm Tongfu Microelectronics, which handles the 3D-stack assembly (tbsnews · F201). China’s first 3D-packaged HBM die — an 8-layer HBM2 stack of 8GB — reportedly dates to mid-to-late May 2023 at Tongfu (fxbaogao · F340). By then the market leaders were already shipping HBM3E in 8-high and 12-high stacks to Nvidia, AMD, Google and AWS — which is why analysts place CXMT roughly three generations behind (ChinaTalk · F66).
The newer milestone is HBM3. Around September 2025, CXMT delivered 16nm-process HBM3 samples to Huawei and ecosystem partners. They are built on the same self-developed G4 DDR5 process, as 8-high stacked DRAM at 6,400 Mbps using MR-MUF packaging (the same family SK Hynix uses), with the vertical-stack thermo-compression bonding outsourced to OSATs (eet-china · F513; dram.com.cn · F341). CXMT originally targeted HBM3 mass production in 2026 — reporting variously cited first-half 2026, Q4-2026, or “later 2026 into 2027” (ChinaTalk · F67; eet-china · F513). By April 2026 that timeline had slipped: Korean media and DigiTimes judged full HBM3 mass production unlikely within 2026, citing back-end stacking, bonding and warpage-yield problems and slow package-yield learning. CXMT is now reported to be re-focusing on HBM3E and 12-layer HBM for 2027 to close the gap to SK Hynix and Samsung to roughly two years, with HBM2E pilot/early mass production as a 2026 bridge product and an HBM allocation of ~60,000 wafers a month (~20% of a targeted 300,000-WSPM 2026 total) (DigiTimes · F1039).
Yield is the open question. A Chinese HBM expert briefing put CXMT’s HBM2 bare-wafer yield at about 83%, packaging yield at about 72%, and final-product yield at only 50-60%, versus roughly 85% packaging yield at the international leaders (fxbaogao · F325). For HBM3, institutional data reportedly put early-development yield at just 30-40% against the 70-80% commercial pass line (eefocus · F326). Chinese reporting claims the later HBM3 samples to Huawei were 12-high stacks reaching about 89% yield by end-2025 — though for context, Samsung and SK Hynix run HBM3 yields above 95% after two-plus years of mass production (zhihu · F514). These yield figures are medium-confidence, drawn from Chinese-language expert transcripts rather than teardowns, and should be read as directional.
CXMT’s intent is not in doubt. It has filed almost 130 HBM-related patents across the US, China and Taiwan — 14 in 2022, 46 in 2023, 69 in 2024 — including filings on hybrid-bonding packaging and HBM3 enabling technology (Reuters/tbsnews · F216).
The frontier CXMT is chasing has meanwhile pulled further ahead. By June 2026, Nvidia’s Vera Rubin was in full production with Samsung, SK Hynix and Micron all certified for HBM4 (>10 Gb/s, above the 8 Gb/s JEDEC base); SK Hynix held the bulk of Vera Rubin’s HBM4 allocation and ~57% of overall HBM revenue, and Samsung shipped industry-first HBM4E samples (3.6 TB/s) on 30 May 2026. That puts CXMT roughly two HBM generations and ~3-4 years behind: it is shipping/sampling HBM2 and HBM3 while SK Hynix, Samsung and Micron are all certified on HBM4 (>10 Gb/s) in full production and Samsung has already sampled HBM4E (Counterpoint/Korean media · F215; Counterpoint · F494). Against HBM4-in-production, CXMT targeting HBM3/HBM3E for 2026-27 and 12-high for 2027 leaves a roughly two-generation, two-year-plus gap (Yahoo Finance · F1130).
HBM’s hardest step is not the DRAM die but the stacking — vertically bonding dies with through-silicon vias at high yield. China’s advantage here flows from NAND. YMTC’s wafer-to-wafer Xtacking hybrid bonding, proven at scale in 3D NAND, is being pointed at HBM: YMTC and CXMT are reportedly eyeing a collaboration that pairs YMTC’s bonding expertise with CXMT’s DRAM know-how (Tom’s Hardware · F217). Chinese reporting goes further, saying CXMT outsourced its HBM3 thermo-compression hybrid-bonding step to YMTC, which lifted initial hybrid-bond yield from about 60% to about 89% over roughly three months — a medium-confidence claim from Chinese analyses (eefocus · F326).
A dedicated packaging and capacity base is forming around this:
Rather than wait on CXMT, Huawei is designing its own HBM. At Huawei Connect on 18 September 2025, it detailed two in-house parts: HiBL 1.0 (128GB, 1.6 TB/s, roughly HBM2e-class), targeted for the Ascend 950PR in early 2026 for prefill and recommendation workloads, and HiZQ 2.0 (144GB, 4 TB/s, roughly HBM3-class), bound for the 950DT in Q4 2026 for decode and training (mydrivers · F531). These were part of Huawei’s first official three-year Ascend roadmap — 950 in early 2026, 960 in 2027, 970 in 2028 — and signal an intent to break the dependence on Korean and US memory (mydrivers · F531). The roadmap is no longer just a target: on 20 March 2026, Huawei launched the Ascend 950PR on the Atlas 350 card at its China Partner Conference — the first product to carry its own HBM (HiBL 1.0), 128GB at ~1.6 TB/s, with mass production beginning the following month (April 2026; see D2); the 950DT (Q4-2026) raises that to 144GB at ~4 TB/s, both targeting ~1 PFLOP FP8 / ~2 PFLOPS FP4, with the Atlas 350 claimed at 1.56 PFLOPS FP4 (~2.8x Nvidia’s H20) (TrendForce · F1047). The “in-house” label refers to Huawei’s design ownership; the DRAM and stacking still flow through the domestic CXMT/YMTC/Tongfu supply chain described above, and domestic HBM supply (CXMT ~2M stacks in 2026) remains the binding limit on total Ascend output (TrendForce · F1047).
On 2 December 2024, the US Bureau of Industry and Security imposed country-wide export controls on advanced HBM to China through a new export classification, ECCN 3A090.c. It controls any HBM stack with a “memory bandwidth density” greater than 2 GB/s per square millimeter — the package’s bandwidth divided by its area — and BIS states that all HBM currently in production exceeds that threshold, making it a de facto ban (BIS · F12). A narrow License Exception HBM carve-out covers only items under 3.3 GB/s/mm² shipped from US- or allied-headquartered firms, which in practice excuses little beyond HBM2 from US companies (BIS · F12). The rule forces China onto domestic HBM precisely when its domestic HBM is three generations behind.
The arithmetic is the crux of the capability-then-investment argument. SemiAnalysis quantifies CXMT’s HBM as a small slice of its DRAM wafers: only about 5,000 wafers a month, out of roughly 265,000 total at end-2025, went to HBM, rising to about 30,000 by end-2026 and about 55,000 by end-2027 (SemiAnalysis · F781; AI Frontiers · F669). SemiAnalysis’s early-2026 read holds the headline math: China can produce ~7 million (primarily HBM3) DRAM dies in 2026 — enough for ~600,000 H100-class chips at 8 stacks each and ~70% yield — of which CXMT’s ~2 million HBM stacks support only about 250,000-300,000 Ascend-910C-equivalent packages (SemiAnalysis · F1085). Logic is not the constraint: SMIC can supply die for more than 1 million Ascend chips a year, and if every leading-edge logic die could be paired with HBM, 2026 Ascend output would exceed 5 million units (SemiAnalysis · F668). Domestic HBM caps assembled units under 300,000 once the foreign stockpile runs out — and the inflection has now landed: as of early 2026 the TSMC die-bank that previously fed Ascend production is effectively exhausted, so future output depends entirely on SMIC wafers plus domestic packaging and domestic (CXMT/Huawei) HBM (SemiAnalysis · F1085). HBM, not logic, is the binding constraint.
Figure 4 — Domestic HBM, not SMIC logic, caps 2026 Huawei Ascend
output at ~250,000–300,000 units versus a >5 million-unit logic
ceiling — an order-of-magnitude cut. The ~2M-stack / 250–300k estimate
is a SemiAnalysis central case, reaffirmed in early 2026 (F1085),
and disputed by other analysts (see Section 6 table and F1039).
Source: SemiAnalysis
· F668; F1085.
That stockpile was large. SemiAnalysis and AI Frontiers estimate China accumulated roughly 13 million foreign HBM stacks — primarily Samsung — before Beijing’s September 2025 directive tightened controls. Huawei and Baidu held about 6 million Samsung stacks (enough for roughly 1.6 million Ascend 910C) plus about 7 million more acquired in the month between the rule’s announcement and its implementation (AI Frontiers · F669). That buffer bridged 2025, but it is finite.
Figure 5 — China’s ~13M foreign-HBM stockpile (6M over the signaling
window + 7M in the one-month pre-rule gap) was a one-time fuel tank, not
a supply: at ~8 stacks per 910C it built ~1.6M packages, but once it
empties (early 2026) domestic CXMT HBM caps Ascend output at <300k
units/yr — roughly 3x below the >1M-unit/yr SMIC logic ceiling.
Source: AI
Frontiers · F232; NextPlatform/Reuters
· F25; SemiAnalysis
· F177; SemiAnalysis
CloudMatrix · F219; Tom’s
Hardware · F287.
The clearest signal of how Chinese officials read the bottleneck came in August 2025 trade talks, when China asked for relaxed HBM restrictions — not lithography relief — pointing to what they see as the tightest constraint (SemiAnalysis · F781). The control regime itself has held on substance but eased diplomatically: the Dec-2024 BIS rule still bans HBM2E/HBM3/HBM3E/HBM4 (permitting only HBM2), but a planned addition of CXMT to the Entity List, reportedly weighed in May 2025, was shelved amid trade talks, and BIS suspended the 50% Affiliates Rule for one year in November 2025. Equipment analysts note CXMT likely secured enough HBM tooling through 2026-2027 — after which sustaining and advancing HBM capacity without Western tools is the unresolved question (AI Frontiers · F1079).
The 2-million-stack figure is contested, and should be flagged as such. It is a SemiAnalysis central-case estimate, and second sources disagree on whether 2026 mass production happens at all (DigiTimes/TrendForce/SemiAnalysis/Morgan Stanley · F756):
| View | 2026 CXMT HBM read | Source |
|---|---|---|
| SemiAnalysis (central case) | ~2M stacks; HBM3 8-hi yields modeled at only ~35% front-end / 70% back-end; possible pivot to skip HBM3 for HBM3E in 2027; figure reaffirmed early-2026 | (SemiAnalysis · F1085; F756) |
| DigiTimes (Apr 2026) | Full HBM3 mass production “unlikely within 2026” on back-end stacking/bonding/warpage yield; pivot to HBM3E + 12-hi for 2027; HBM2E bridge in early 2026 | (DigiTimes · F1039) |
| TrendForce (Jan 2026) | Only a pilot line at the existing fab; volume HBM planned for a future Shanghai facility | (TrendForce · F756) |
| Morgan Stanley (channel check) | Upside: HBM capacity could reach ~100,000 wafers/month by end-2026 (~20% of a 300k total) | (Morgan Stanley · F756) |
| AI Frontiers (optimistic) | ~7 million HBM3 dies in 2026 (~600k H100-class chips at 70% yield) | (AI Frontiers · F669) |
The range — from “no meaningful 2026 production” to “100k wafers a month” — is wide. CXMT is building a dedicated back-end HBM plant in Shanghai targeting an initial ~30,000 HBM wafers a month, with start-up slipped to end-2026, plus ~60,000 a month of HBM3 front-end capacity carved out of the Hefei and Beijing fabs (zhihu · F363). The broader Shanghai DRAM fab — with capacity up to ~3x the Hefei headquarters and what SemiAnalysis estimates could be 400,000+ WSPM at full ramp — begins equipment installation in 2026 with full-scale server/PC/automotive DRAM mass production planned for H1-2027; dedicated HBM-packaging subsidiaries are being stood up separately in Shanghai, reflecting the disaggregated front-end-die / back-end-stack model in which OSATs (JCET, Tongfu) handle TSV and stacking for CXMT’s front-end HBM wafers (The Economy · F1043). The direction is not in dispute: even the optimistic reads leave China’s domestic HBM output well short of what its logic supply could otherwise feed. The constraint is real; only its exact tightness in 2026 is uncertain.
US export controls shape every other part of this story. They decide which chips China can buy, which tools its fabs can run, which foreign foundries will take its orders, and — increasingly — whether a Chinese firm can rent compute it does not own. Since October 2022 the rules have moved in a tight loop: each rule closes a specific workaround, China and its suppliers find the next least-controlled path, and the next rule closes that (Congressional synthesis · F816). Two points matter for the capability-then-investment thesis. First, the binding constraint is not a single ban but a legal architecture — the Foreign Direct Product (FDP) rule — that reaches output from fabs anywhere on Earth as long as they run on US tools or US chip-design software (BIS FDP rule, EAR 734.9 · F643). Second, the controls are de-globalizing China’s supply chain from both ends at once: foreign toolmakers are losing their largest market while Chinese foundries lose their foreign customers (SMIC FY2025 results · F1030). That double squeeze is what forces the indigenous-investment response the rest of this report traces.
The regime is best understood as four foundational events, each building on the last.
7 October 2022 — the foundation. A Bureau of Industry and Security (BIS) interim final rule, published in the Federal Register as 87 FR 62186, created the modern controls. It established two new Export Control Classification Numbers (ECCNs) — 3A090 for advanced computing integrated circuits and 4A090 for the computers built from them — and added fab-level end-use controls (codified at EAR 744.23) targeting any facility in China producing logic at the 16/14nm node or below, DRAM at an 18nm half-pitch or tighter, or NAND flash with 128 or more layers (Federal Register, Oct 2022 IFR · F69). “Half-pitch” is the spacing between memory cells; a smaller number means a denser, more advanced chip.
The same rule added a novel weapon: a US-person restriction at EAR 744.6(c). Without a license, no US person — citizen, green-card holder, or US-incorporated entity — could support the development or production of ICs at the targeted Chinese fabs, even when no US-controlled item was involved and even without knowledge that the fab met the criteria (Federal Register, Oct 2022 IFR · F629). The provision took effect 12 October 2022 and forced US-citizen and green-card executives and engineers to resign from or stop servicing leading-edge Chinese fabs — YMTC, CXMT, SMIC — within days (Federal Register, Oct 2022 IFR · F629).
17 October 2023 — closing the workaround. The 2022 rule screened advanced-computing chips on interconnect bandwidth, so Nvidia shipped throttled A800 and H800 parts with the interconnect cut but the compute intact. The 2023 update replaced that metric with a two-pronged test built on Total Processing Performance (TPP) — a measure of raw compute throughput — and performance density (TPP per unit of die area). Any datacenter chip with a TPP of roughly 4,800 or above was caught outright, which ended the A800/H800 escape and also swept in the A100, H100, L40, L40S, and even the consumer RTX 4090 (Federal Register, Oct 2023 · F70).
The rule split ECCN 3A090 into two tiers. 3A090.a is the regular-license tier, reviewed under a presumption of denial, capturing chips with TPP at or above 4,800, or TPP at or above 1,600 combined with a performance density at or above 5.92. The new 3A090.b is a “gray zone” for less-advanced but still AI-capable datacenter chips: TPP of 2,400–4,799 with performance density of 1.6–5.91, or TPP at or above 1,600 with density of 3.2–5.91 (Federal Register, Oct 2023 · F631). The performance-density screen defeated a specific workaround: clustering many small, individually-compliant chips into one powerful system. Gray-zone .b items can ship under a new License Exception NAC (Notified Advanced Computing), under which the exporter notifies BIS and BIS decides within 25 days whether a license is required (Federal Register, Oct 2023 · F631).
2 December 2024 — the master package. This is the densest single action in the regime. BIS issued companion rules that, together: added 140 entities to the Entity List, modified 14 existing China entries, and assigned 16 entities the new Footnote 5 designation (BIS press release, Dec 2024 · F21); placed new license requirements on 24 types of semiconductor manufacturing equipment (SME) plus 3 software tools, spanning etch, deposition, lithography, ion implantation, annealing, metrology/inspection and cleaning (BIS press release, Dec 2024 · F19); created a new ECCN 3A090.c to control high-bandwidth memory (Section 3); and added two new FDP rules to EAR 734.9 (Section 2) (Federal Register 2024-28270 · F635). Three Chinese firms — AMEC, CSMC, and Hua Hong Grace — were removed from the Validated End-User (VEU) program (BIS press release, Dec 2024 · F21).
2025-2026 — the H20 ban, the reversal, the Busan truce, and the H200 opening. On 9 April 2025 BIS notified Nvidia that exporting the H20 — its most advanced China-legal part — to China, Hong Kong, Macau and the D:5 country group now required a license, citing supercomputer-diversion risk; on 14 April BIS made the requirement indefinite (Nvidia Form 8-K, Q1 FY26 · F682). Nvidia took a US$4.5 billion charge on excess H20 inventory and purchase commitments and disclosed roughly US$2.5 billion of foregone Q1 revenue; H20 sales had been US$4.6 billion that quarter before the ban (Nvidia Form 8-K, Q1 FY26 · F114). AMD’s MI308 was covered in parallel. Then in July 2025 the Trump administration reversed course, and in August the two firms agreed to remit 15% of their China AI-chip sales revenue to the US government in exchange for licenses — an arrangement Nvidia itself flagged as legally vulnerable under the Constitution’s export-tax clause (CNN, Aug 2025 · F115). Nvidia later confirmed the 15% share was never codified in any regulation — Washington merely expressed an expectation of receiving it, leaving the legal basis unclear (Nvidia Q2 FY26 · F1071).
The arc then turned on the Trump-Xi Busan summit (30 October 2025), which produced a coordinated mutual de-escalation: it underpinned the BIS 13 January 2026 shift of H200/MI325X-class licensing to case-by-case review and the one-year suspension of the 50% Affiliates Rule on the US side, and triggered China’s matching suspensions of its gallium/germanium/antimony and rare-earth controls on the China side — pausing the expansion of both architectures without dismantling them, with analysts cautioning the suspensions are reversible after their one-year windows (Busan truce, CNBC · F1058). Following Trump’s 8 December 2025 announcement allowing H200-and-similar exports, Commerce cleared roughly 10 Chinese firms — including Alibaba, Tencent and ByteDance — to buy Nvidia H200 chips, capped at 75,000 units per customer, with the revenue cut raised to 25% (from 15% for the H20) and paired with a 25% Section 232 tariff announced 14 January 2026 on semiconductors meeting the same TPP<21,000 / DRAM-bandwidth<6,500 GB/s thresholds used in the new BIS licensing rule (Trump H200 clearance · F1066; Section 232 tariff · F1078). As of mid-2026, no H200 deliveries to China had occurred: the deal sat in legal limbo amid US-China rivalry and Beijing’s own new rules barring foreign AI chips from state-funded datacenters, with Jensen Huang eyeing a possible breakthrough around Trump’s May-2026 China state visit (Trump H200 clearance · F1066). Nvidia’s filing for the quarter ending April 2026 confirmed zero Data Center Hopper shipments to China, versus US$4.6 billion a year earlier, and China fell to ~5.9% of Nvidia revenue in Q2 FY2026 (vs a ~15% prior-10-quarter average) and to 13% of FY2025 (from 21% in FY2023) (Nvidia Q2 FY26 · F1071). Blackwell remained blocked from China (CNN, Aug 2025 · F115).
One mechanism defines the regime: the FDP rule. A simple value-based de minimis test — does the item contain more than 25% US content? — is easy to engineer around. The FDP rule sidesteps that test. It extends US export jurisdiction to a foreign-made item when either the item is itself the direct product of specified US-origin technology or software, or the item is produced by a plant whose major component is itself a direct product of US technology (Covington analysis · F205). This is a master key rather than a side door because US-origin intellectual property does not count toward de minimis, but US tooling does — and BIS presumes any advanced IC is produced using at least one US major-component tool (Covington analysis · F205).
The December 2024 rule formalized two FDP rules — the Advanced Computing FDP at EAR 734.9(h) and the SME FDP at 734.9(i) — that combine the product-or-plant test with a product scope (3A090/4A090 chips or listed equipment) and a destination nexus to China, Macau, or Entity-List parties (BIS FDP rule, EAR 734.9 · F643). Every leading-edge fab on Earth — TSMC, Samsung, SK Hynix — runs on US-origin EDA software from Synopsys and Cadence and US tools from Applied Materials, Lam, and KLA. Their advanced output therefore falls under the Export Administration Regulations even with zero US physical content, and the de minimis escape simply does not apply (BIS FDP rule, EAR 734.9 · F643). “EDA” is electronic design automation — the software used to design and verify a chip before it is fabricated.
This is the legal hook behind the Sophgo/Huawei case, the textbook FDP enforcement action. A TechInsights teardown of a Huawei Ascend 910B found a TSMC-made die matching a design ordered by Sophgo, a Chinese chip firm and Bitmain affiliate; TSMC reported it to Commerce in October 2024 and suspended Sophgo shipments (BIS final rule, 16 Jan 2025 · F649). On 16 January 2025 BIS added the Sophgo corporate family — 14 China and 2 Singapore units — plus LLM developer Zhipu AI to the Entity List (BIS final rule, 16 Jan 2025 · F649). A TSMC-fabbed 3A090 die diverted to an Entity-Listed Chinese end-user is exactly the violation the FDP rule was written to catch (BIS FDP rule, EAR 734.9 · F643). The same logic now reaches Huawei’s own silicon: in May 2025 BIS issued guidance that using a Huawei Ascend 910B, 910C, or 910D anywhere in the world violates the EAR via General Prohibition 10, because a China-headquartered 3A090 chip was likely produced in violation of the rules (Baker McKenzie analysis · F288).
High-bandwidth memory (HBM) — the stacked DRAM that feeds an AI accelerator — is the choke point the December 2024 rule was built around, because China’s indigenous AI chips depend on imported HBM. The new ECCN 3A090.c controls standalone HBM with a memory bandwidth density above 2 GB/s per square millimeter (the stack’s bandwidth divided by its package area). The rule’s own text notes that all HBM stacks currently in production exceed this threshold, so it functionally bans HBM2 and above to China and Macau (Federal Register 2024-28270 · F635). A License Exception HBM permits only items below 3.3 GB/s/mm2 and only for US- or allied-headquartered exporters, and the control reaches non-US HBM through the Advanced Computing FDP rule at EAR 734.9(h) (Federal Register 2024-28270 · F635; Covington analysis · F20).
On the equipment side, the central new mechanism is the Footnote 5 (FN5) designation. An FN5-listed advanced-node fab triggers the expanded SME FDP rule, so foreign-made tools that are the direct product of US technology — or made by plants using US-origin major-component tools — need a license to reach it (BIS final rule, Dec 2024 · F710). FN5 is the equipment-side analogue of the Advanced Computing FDP rule, widening the extraterritorial reach to tools, not just finished silicon (BIS final rule, Dec 2024 · F710). The 16 FN5 entities include affiliates of SMIC, SwaySure, PXW, and Fujian Jinhua (JHICC) (Morgan Lewis analysis · F206). On 5 December 2024 BIS added SwaySure Technology and Shenzhen Pengxinxu, both with the FN5 designation and a presumption of denial, citing risk of supporting Huawei’s indigenous advanced-node ambitions (Federal Register, Entity List, Dec 2024 · F764).
The Entity List is the regime’s named-target instrument, and its focus has shifted over time. The October 2023 wave was GPU-focused: BIS added 13 entities — the Biren Technology and Moore Threads corporate families — cutting both Chinese GPU designers off from TSMC fabrication and halting Biren’s BR100 mid-ramp (BIS final rule, 19 Oct 2023 · F645). The December 2024 listings tilted instead toward equipment makers and advanced-node producers, including Shenzhen SiCarrier — the Huawei-linked broad SME house whose entry names “Huawei Starlight Engineering Department” as an alias (BIS final rule, 5 Dec 2024 · F661).
The list’s reach is also widening structurally. On 30 September 2025 BIS published the 50% Affiliates Rule (effective 29 September), which automatically subjects any entity owned 50% or more — directly or indirectly, individually or in aggregate — by Entity List, Military End User, or most SDN-listed parties to the same restrictions, closing the loophole where only specifically named entities were caught despite extensive corporate ties (Squire Patton Boggs analysis · F289). As part of the Busan-truce de-escalation package — mirroring China’s same-week suspension of its Ga/Ge/Sb ban — BIS suspended the rule on 10 November 2025 for one year, resetting activation to 10 November 2026; as of mid-2026 it remained dormant, and if it activates on schedule it would dramatically widen Entity-List coverage to thousands of majority-owned subsidiaries of listed Chinese entities (Affiliates Rule suspension, CSIS · F1083). Separately, BIS kept adding named entities through 2025: a 42-entity wave in March 2025 (within an 80-entity multi-country action) and 23 PRC entities in September 2025 — 13 tied directly to China’s IC industry, with Shanghai Fudan Microelectronics and Sino IC Technology placed under additional FDP-rule restrictions — taking Chinese Entity-List entries past 1,065, nearly a third of all entries (CRS R48642 · F1195). A separate 2025 effort, the Framework for AI Diffusion (published 15 January 2025), would have partitioned the world into three tiers for AI-chip access, but BIS rescinded it on 13 May 2025 before it took effect; China was always in the prohibited Tier 3, so the rescission did not change China’s direct treatment (BIS interim final rule, 15 Jan 2025 · F687).
Unilateral US controls leak unless the other two pillars of the equipment world move in step: the Netherlands (ASML) and Japan (Tokyo Electron, Nikon, Screen, Advantest). Both did, though each framed its action as country-neutral national policy rather than alignment with Washington.
The Netherlands progressively brought ASML’s deep-ultraviolet (DUV) immersion lithography tools under its own national license regime. Extreme-ultraviolet (EUV) systems had already been barred to China since 2019; DUV is the older but still capable generation used for 7nm-class chips via multi-patterning (ASML press release, Sep 2024 · F156). From 1 September 2023 the Dutch required licenses for the newer NXT:2000i and later immersion systems; from 7 September 2024 they extended licensing to the older 1970i and 1980i tools, which ASML characterized as a transfer of licensing authority from the US to the Netherlands (ASML press release, Sep 2024 · F156). On 1 January 2024 the Dutch government partially revoked an existing license, blocking some NXT:2050i/2100i shipments to a handful of Chinese fabs (ASML statement, Sep 2024 · F665). The stakes for ASML are large: China was its single largest market at roughly 49% of Q2 2024 lithography-system revenue (ASML statement, Sep 2024 · F665). The Dutch ratchet continued: effective 1 April 2026 — the third tightening since 2023 — the Netherlands moved ASML fully onto Dutch (CDIU) licensing rather than US authority and expanded the controlled list to specific measurement and inspection tools from Dutch firms; controls remain country-neutral and case-by-case, with only EU-sanctions-list or US-Entity-List parties facing automatic restriction. The exposure is material — China was ~60% of ASML’s 2024 lithography unit volume and ~25% of its global servicing business, and ~US$3 billion of 2024 ASML sales went to Chinese entities of concern (Netherlands Apr-2026 tightening · F1093).
Japan’s METI imposed license requirements on 23 categories of advanced SME effective 23 July 2023, covering epitaxy, deposition, etch, heat-treatment, cleaning, photomask, and ArF-DUV-and-better lithography tools; 42 Wassenaar Arrangement partners get simplified licensing while China and roughly 160 other destinations do not (Hogan Lovells analysis · F157). Japan then kept ratcheting: METI added 21 further items in April 2024, and a January 2025 update broadened the scope beyond tools to include chip testing and metrology equipment, EDA software, materials, and finished chips, with explicit targeting of 14nm-and-below manufacturing (CSIS translation · F703). In November 2025 Japan went further into materials, placing 12 core semiconductor inputs — including high-end ArF/EUV photoresists — on its export-control list restricting supply to 42 Chinese firms, acute leverage given Japan controls over 70% of world photoresist and essentially all sub-7nm EUV photoresist. Beijing’s most concrete reply came in April 2026, when MOFCOM added 40 Japanese companies to its export-control and unreliable-entity lists — a hardening US-Japan-Netherlands “iron triangle” on materials and equipment, met by targeted Chinese entity-listing of Japanese firms (China +40 Japanese firms, CSIS · F1165).
Beijing has answered with a coordinated toolkit aimed at upstream chokepoints and at US firms operating inside China.
The headline measure is MOFCOM Announcement 2024 No.46 (3 December 2024), issued one day after the US 140-entity action. Its structure matters: Article 1 is a blanket prohibition on exporting dual-use items to US military end-users or for military end-uses, while Article 2 sets a presumption of denial (“in principle, licenses will not be granted”) for exports to the US of gallium, germanium, antimony, and superhard materials, plus stricter end-use review of graphite (MOFCOM No.46, CSET translation · F609). The leverage is real: China holds roughly 99% of refined gallium, about 60% of refined germanium, and around half of mined antimony (MOFCOM No.46, CSET translation · F116). The US Geological Survey estimated the gallium/germanium ban alone could cost the US economy around US$3.4 billion (MOFCOM No.46, CSET translation · F116). On 9 November 2025 MOFCOM Announcement No.72 suspended Article 2 until 27 November 2026 — directly implementing the 30 October 2025 Trump-Xi Busan truce and arriving alongside a parallel 7 November one-year suspension of the October-2025 rare-earth/battery-mineral controls — restoring gallium, germanium, antimony, superhard materials and the tightened graphite review to China’s standard licensing framework. The critical caveat: Article 1 of No.46 (the blanket ban on dual-use exports to US military end-users/end-uses) remains in full effect, and the suspension is temporary — Beijing can reinstate the controls after 27 November 2026 (MOFCOM No.72 suspension, CNBC · F1052; MOFCOM No.46, CSET translation · F609).
China extended the same long-arm logic to rare earths in 2025. MOFCOM Announcement 2025 No.61 (effective 9 October 2025) imposed extraterritorial controls: any foreign-made product containing China-origin rare earth at a 0.1% value share or more requires an export license, and items made abroad using China-origin rare-earth processing technology are also captured (Allbright Law analysis · F367). The single 0.1% threshold is far more aggressive than the US 10%/25% de minimis tests (Allbright Law analysis · F367). Article 4 of No.61 mirrors the US controls precisely: rare-earth applications face case-by-case approval when the end use is R&D or production of 14nm-and-below logic or 256-layer-and-above memory chips, the equipment and materials for such processes, or AI with potential military applications (Allbright Law analysis · F372).
Beyond materials, Beijing uses domestic regulatory reviews as retaliation. In May 2023 the Cyberspace Administration of China (CAC) barred Micron products from critical information infrastructure after a network-security review — the template for using security reviews against US memory suppliers (DigiChina/Stanford · F123). In December 2024 the State Administration for Market Regulation (SAMR) opened an antimonopoly probe into Nvidia over conditions attached to its 2020 US$6.9 billion Mellanox acquisition; in September 2025 SAMR announced a preliminary finding that Nvidia had violated the antitrust law, with potential fines of 1–10% of prior-year China revenue (roughly US$17 billion in the year ending January 2025, implying up to about US$1.7 billion) (Jurist · F124).
The sharpest 2025-26 demonstration of China’s supply-chain leverage was the Nexperia standoff. After the Dutch government invoked a Cold-War-era statute on 30 September 2025 to place Nexperia (a Dutch-headquartered chipmaker owned by China’s Wingtech) under state supervision and a court suspended its Wingtech-appointed executives, China retaliated by briefly blocking exports of China-made Nexperia chips — hitting the auto sector hardest (Honda guided a ~US$960 million operating-profit hit for the year to March 2026). By mid-November 2025 the Netherlands suspended its state control and China walked back the export block, but as of early 2026 the European and Chinese Nexperia entities had not reunited, with a Dutch Enterprise Chamber hearing set for 14 January 2026 on a possible formal mismanagement probe — the dispute carrying into 2026 unresolved (Nexperia dispute, Automotive News · F1048).
Stepping back from any single action, the leverage is profoundly asymmetric. On the inputs that actually gate advanced manufacturing, China is near-zero self-sufficient and the foreign holder is near-total: metrology (KLA’s largest Chinese rival is under 1% of the China market), EUV mask optics (Zeiss SMT near-monopoly), compliant HBM (~0% domestic against SK Hynix/Samsung/Micron), probe cards, ArF photoresist, EDA physical verification (Siemens Calibre in over 90% of Chinese designers), and ABF substrate. China’s one genuinely hard counter-chokepoint sits a layer upstream, in mineral refining — gallium, germanium, and antimony — which is exactly why MOFCOM No.46 reached for those minerals rather than for any finished good.
Figure 2 — On six front-end chokepoints China is near-zero
self-sufficient while foreign supply is near-total (red); its one hard
counter is mineral refining — gallium ~98%, germanium ~68%, antimony
~48% (green, inverted). HBM split is 2024 basis; other figures
2023-2025. Source: KLA
process control · F627; Zeiss
EUV optics · F305; SK
Hynix HBM · F215; Probe cards ·
F622; ArF
photoresist · F409; Siemens
EDA · F200; ABF
substrate · F502; USGS minerals ·
F717.
The controls are pulling the China supply chain apart from both ends, and the two effects are one coin.
On the demand-into-China side, China is the world’s largest equipment market — roughly 40% of global wafer-fab-equipment (WFE) spending in 2024, with SEMI reporting a record ~US$49.5 billion of total China equipment investment, ahead of Korea (~20%), Taiwan (10–20%), and the US (~10%) (SEMI/Yole · F714). Yet only about 5% of WFE is manufactured in China. The gap between 40% of demand and 5% of supply is the entire import-substitution opportunity (SEMI/Yole · F714). Controls are shrinking foreign toolmakers’ share of that pool: their China revenue shares have fallen roughly 7–10 points, to the 28–35% range (SMIC FY2025 results · F1030).
| Foreign toolmaker | China share of revenue |
|---|---|
| Tokyo Electron (TEL) | ~35% |
| Lam Research | ~34% |
| ASML | ~33% |
| KLA | ~33% |
| Applied Materials (AMAT) | ~28% |
On the supply-out-of-China side, the same regime pushes Chinese foundries out of Western customers. China was 87.6% of SMIC’s Q4 2025 revenue per its official FY2025 results, up from already-high levels as Huawei demand, domestic-fabless demand, and US-customer attrition concentrated its order book (SMIC FY2025 results · F1030). The result is a bifurcated, China-for-China stack: foreign toolmakers lose China headroom while Chinese foundries lose foreign customers (SMIC FY2025 results · F1030).
Figure 1 — The two effects are one coin: the five WFE toolmakers’
China revenue share dropped ~7-10 points (to the 28-35% range) in
FY2025, while SMIC’s revenue concentrated to ~88% China. Source: company
filings · F963; SMIC FY2025
results · F1030.
The gap between the rules on paper and the chips on the ground is where enforcement and evasion meet.
Penalties have escalated sharply. In April 2023 BIS imposed a US$300 million civil penalty on Seagate — its largest standalone administrative penalty — for selling 7.4 million foreign-produced hard drives to Huawei across 429 transactions worth ~US$1.1 billion, in violation of the FDP rule because the drives were made on equipment that was a direct product of US technology (Paul Weiss analysis · F751). In July 2025 Cadence agreed to plead guilty and pay over US$140 million for routing EDA tools to the Entity-Listed National University of Defense Technology via front companies between 2015 and 2021 (DOJ press release · F862); in April 2026 BIS closed the loop with a parallel administrative settlement in which Cadence admitted its Chinese-subsidiary employees knowingly transferred sensitive US technology to NUDT, Phytium and other Entity-List parties tied to military and nuclear-weapons supercomputing programs (Cadence BIS settlement, CRS R48642 · F1198). In February 2026 Applied Materials settled with BIS for US$252.5 million over China shipments routed through a South Korea subsidiary to SMIC, with the parallel DOJ and SEC investigations closed without action (Applied Materials 8-K · F886). The largest exposure of all is TSMC’s: Reuters reported in April 2025 that the foundry could face a penalty of US$1 billion or more over the Sophgo die that reached Huawei, because the EAR caps penalties at up to twice the value of each unauthorized transaction and a RAND researcher estimated TSMC made nearly 3 million chips matching the Sophgo design (Reuters · F857).
Evasion has been relentless and follows the ratchet. Pre-deadline stockpiling is a recurring time-arbitrage: SemiAnalysis found Samsung alone supplied ~11.4 million HBM stacks to China, including ~7 million in the single month between the 2 December 2024 HBM-control announcement and the 31 December compliance date — enough, with other channels, for roughly 1.6 million Ascend 910C packages (SemiAnalysis · F858). Physical smuggling runs through Singapore, Malaysia, Hong Kong, and Thailand: Fortune reported that over US$1 billion in controlled Nvidia chips moved into China in a single three-month window in 2025 (Fortune · F738); a US$390 million server scheme led to charges in Singapore in March 2025 (TechCrunch · F728); and in March 2026 the SDNY charged a Super Micro co-founder over a scheme that diverted ~US$2.5 billion of GPU servers to China, complete with warehouses of dummy servers staged to fool compliance auditors (CNN · F815).
As physical smuggling drew enforcement, evasion shifted to offshore cloud rental — using controlled chips abroad without ever importing one. Tencent accesses banned Nvidia Blackwell systems via Japanese operator Datasection running hardware in Japan and Australia, in rental deals worth over US$1.2 billion, and Shanghai’s INF Tech allegedly rented 2,300 banned GPUs from an Indonesian telco (wccftech · F780). Washington is now closing that vector too: the House passed the Remote Access Security Act 369-22 on 12 January 2026 to treat remote access to controlled chips as itself subject to export law (The Register · F783), and on 31 May 2026 BIS guidance shifted the test from where the chip ships to who owns the buyer — China-headquartered firms now need licenses for Blackwell, Rubin, and MI350X chips even when deployed outside China (ABHS analysis · F952). Meanwhile, BIS formally eased the China licensing posture for H200-equivalent chips from presumption of denial to case-by-case review on 13 January 2026, even as it expanded ownership-based control — tightening the structure while loosening the headline (Morgan Lewis analysis · F920).
China’s drive to make its own chipmaking tools — the wafer fab equipment, or WFE, that builds chips — has produced a sharply uneven map of wins and gaps. In the high-volume process steps that physically shape the chip, namely etch (carving patterns into the wafer) and deposition (laying down thin films), domestic champions NAURA and AMEC have taken real share. They lifted domestic tool usage in China’s fabs from roughly 25 percent in 2024 to about 35 percent in 2025, past Beijing’s Made-in-China-2025 target (TrendForce · F251; CSIS · F784); on a vendor-revenue basis the localization rate reached 23.2 percent in 2025, up from 8 percent in 2021 and projected toward ~39 percent by 2030 (Electronics Weekly/Yole · F1200), and Beijing has since set a fresh ~70-percent domestic-equipment target for 2027 (TrendForce · F1174). But the gains sit in a few categories, the headline rate is measured in a way that flatters the picture, and the most strategic front-end category — metrology and inspection, the measurement tools that gate yield — remains an almost untouched foreign monopoly held by KLA. China is winning the localization battle on tonnage and losing it on the bottleneck steps, while domestic vendors fund the fight at razor-thin or negative margins.
Figure 1 — China has localized the easy, high-volume tools (etch, deposition) but the binding, highest-value steps — metrology/inspection and lithography — remain near zero. 2026 data confirms the gradient: front-end metrology/inspection is still the single weakest link at under 10 percent, even as overall vendor-revenue localization reached 23.2 percent in 2025. Source: CSIS · F784; TechNews · F427; Electronics Weekly/Yole · F1200.
Etch and deposition are the two largest WFE categories by spend after lithography, and they are where Chinese tools have displaced the most foreign equipment. NAURA Technology (北方华创), the country’s largest tool maker, booked etch revenue above 8 billion yuan in 2024, up 45 percent year on year, and won more than 60 percent share at major customers SMIC and YMTC; it runs 14nm etch in volume production (about 20 percent of mix) and 5nm in validation (Swiss Transparent · F38). Its thin-film deposition revenue crossed 10 billion yuan for the first time in 2024, up 66.7 percent, and NAURA is the only domestic firm with a full PVD-plus-CVD-plus-ALD portfolio offering atomic-level film control (Swiss Transparent · F39). At group level NAURA closed FY2025 with a record 39.35 billion yuan of revenue, up 30.85 percent (from 27.3 billion yuan over the first three quarters, up 33 percent, where etch and thin-film were already about 70 percent of the mix — 31 percent etch, 40 percent thin-film) (Sina · F323), of which IC-process equipment was 36.73 billion yuan (93.34 percent of the total, up 32.57 percent at a 39.18 percent gross margin); net profit slipped 1.77 percent to 5.52 billion yuan as R&D rose 34.74 percent to 7.28 billion yuan (18.49 percent of sales), and cumulative deliveries of both vertical-furnace and PVD tools each passed 1,000 units. Q1-2026 carried the momentum forward — revenue 10.32 billion yuan, up 25.80 percent, net profit 1.64 billion yuan (+3.42 percent), gross margin rebounding to 40.77 percent — and the company guides FY2026 revenue of 46.79–52.02 billion yuan (cninfo · F315; Sina · F1089; TradingView · F1080). In March 2026 NAURA also launched 12-inch wafer-to-wafer and chip-to-wafer hybrid-bonding tools — entering the HBM and chiplet advanced-packaging core-tool segment — and consolidated the wet-process flow: it took control of coater-developer (track) leader Kingsemi (17.87 percent of equity plus a board majority, jointly covering over 97 percent of the wet-process workflow) and acquired 90 percent of Chengdu Cathay Vacuum (East Money · F1097).
AMEC (中微公司) is the etch specialist. Its plasma etch revenue compounded at over 50 percent a year from 2019 to 2024, and its etch tools now span 55nm down to 5nm, integrated into a 5nm manufacturing supply chain (TrendForce · F50; TrendForce · F51). Chairman Gerald Yin’s claim that 5nm is reachable with DUV (deep-ultraviolet) multi-patterning rather than EUV matters here: it implies etch precision can substitute, in part, for the lithography China cannot buy (TrendForce · F51). AMEC is now pushing into deposition. Its thin-film revenue (LPCVD and ALD) jumped about 1,333 percent year on year to 403 million yuan in the first three quarters of 2025, on total revenue of 8.06 billion yuan, with R&D at 31 percent of sales (TrendForce · F277). The advanced-etch ramp accelerated into 2026: Q1-2026 net profit grew nearly 200 percent year on year, driven by sharply higher shipments of high-end etch tools for advanced-logic mid-stage and ultra-high-aspect-ratio (UHAR) memory etch — its self-developed UHAR etchers now run 300-plus reaction chambers in stable mass production, a next-gen 90:1 low-temperature etcher has shipped for validation, and a second-generation ICP etcher hit a 140:1 aspect ratio in 3D-DRAM (part of the profit gain was a one-off ~397 million yuan from selling part of its Piotech stake) (STCN · F1104). AMEC also moved to close its dry-only gap: in March 2026 it disclosed a 1.576-billion-yuan plan to buy 64.69 percent of CMP maker Hangzhou Zhonggui (杭州众硅), cleared by the STAR Market listing committee by late April, which would give AMEC all four front-end core process capabilities — etch, thin-film deposition, metrology/inspection, and wet (CMP) (Cnstock · F1113).
A second tier fills out the adjacent steps. Piotech (拓荆科技), the deposition pure-play, posted 6.52 billion yuan of 2025 revenue (up 59 percent), led by PECVD at 5.14 billion yuan and ALD up 192 percent; it claims mass-production capability across all five thin-film deposition categories — the only firm globally to do so — and is China’s most complete hard-mask process supplier (Sina · F330; cninfo · F342). In Q1-2026 Piotech revenue rose 56.97 percent to 1.112 billion yuan and net profit swung to 571 million yuan from a 147-million-yuan loss a year earlier, with gross margin up to 41.69 percent on advanced-process tools scaling into mass production — though much of the headline profit was non-recurring fair-value gains (deduct-non-recurring net profit was about 102 million yuan) (IThome · F1119). ACM Research (盛美上海) owns wet-process cleaning, with 2025 revenue of 6.79 billion yuan (up 21 percent) and TEBO megasonic cleaning rated for 1xnm (16–19nm) patterned wafers at aspect ratios up to 60-to-1 (SSE · F375; ACM · F87); consolidated ACM Research lifted Q1-2026 revenue 34.2 percent to 231.3 million USD, reaffirmed FY2026 guidance of 1.08–1.175 billion USD, and trimmed its stake in the Shanghai unit to 73.6 percent ahead of a planned HKEX secondary listing (StockTitan · F1133). Hwatsing (华海清科) dominates domestic CMP (chemical-mechanical planarization, the polishing step), having built China’s first 12-inch CMP machine; CMP and wafer-thinning made up 88 percent of its 3.19 billion yuan of Q1–Q3 2025 revenue (Wikipedia/Bernstein · F89; Sina · F393), and Q1-2026 revenue rose 31.66 percent to 1.201 billion yuan as it broadened into thinning, ion-implant and wet tools, though net profit grew only 5.95 percent on cost outpacing revenue (163 · F1134). Kingsemi (芯源微) covers the coat/develop (track) step and, after NAURA took control in early 2026, will lean on the group to grow front-end chemical-cleaning share (Stockstar · F1143). Industry tallies put local etch-plus-deposition supply above 40 percent of the China market (TrendForce · F251; CSIS · F784).
| Vendor | Segment | Revenue (period) | Growth YoY | Source |
|---|---|---|---|---|
| NAURA | Etch + deposition + furnaces | 39.35bn yuan (FY2025) | +31% | F1089 |
| NAURA | Etch + deposition + furnaces | 10.32bn yuan (Q1 2026) | +26% | F1080 |
| NAURA etch | Etch | >8bn yuan (FY2024) | +45% | F38 |
| NAURA thin-film | Deposition | >10bn yuan (FY2024) | +67% | F39 |
| AMEC | Etch + thin-film | 8.06bn yuan (9M 2025) | +46% | F277 |
| AMEC | Etch + thin-film | net profit +~200% (Q1 2026) | n/a | F1104 |
| Piotech | Deposition + bonding | 6.52bn yuan (FY2025) | +59% | F330 |
| Piotech | Deposition + bonding | 1.11bn yuan (Q1 2026) | +57% | F1119 |
| ACM Research | Cleaning + plating | 6.79bn yuan (FY2025) | +21% | F375 |
| ACM Research (consol., USD) | Cleaning + plating | 231m USD (Q1 2026) | +34% | F1133 |
| Hwatsing | CMP + thinning | 1.20bn yuan (Q1 2026) | +32% | F1134 |
| Skyverse | Metrology + inspection | 2.05bn yuan (FY2025) | +49% | F355 |
| Skyverse | Metrology + inspection | 396m yuan (Q1 2026) | +35% | F1160 |
| Kingsemi | Coat/develop track | 1.95bn yuan (FY2025) | +11% | F428 |
| Accotest | Test/ATE | 1.35bn yuan (FY2025) | +49% | F1151 |
| Changchuan | Test/ATE | 5.29bn yuan (FY2025) | +45% | F1147 |
Scale at home does not mean scale abroad. NAURA’s global etch share, despite its domestic lead, was still only about 3.8 percent in 2024 — even China’s strongest tool maker is small on the world stage outside its own market (Swiss Transparent · F38). The revenue gap puts that in scale: NAURA’s whole FY2025 is roughly one-fifth of a single US incumbent’s, and Applied Materials’ China revenue alone exceeds NAURA, AMEC and ACM Research combined.
Figure 2 — NAURA is ~1/5 of AMAT; AMEC ~1/16; ACM ~1/30 — and AMAT’s China revenue alone (~$8.53B) exceeds all three combined (~$8B). The gap is closing (NAURA +31%/yr vs AMAT +4%) but China’s flagship toolmaker is still a fraction of one US incumbent. Source: NAURA FY2025 · F1089; Applied Materials FY2025 · F1260.
Metrology (precise measurement of dimensions, films, and overlay) and inspection (defect detection) together form “process control” — the eyes of the fab. You cannot raise yield on a new process without measuring what each tool did to the wafer, so process control gates the entire learning curve. This is the category China has barely cracked, and one American company dominates it: KLA.
KLA holds over half the global process-control market. VLSI Research put it at 51 percent in 2020, rising to 55.8 percent in 2023, with the top five firms above 84 percent and no rival above 8 percent — a “one-super-many-strong” (一超多强) structure (eefocus/VLSI · F633). That foreign lock is near-total in metrology: KLA’s China revenue alone (~$4.0B, ~33% of its FY2025) is roughly 3x the entire Chinese domestic metrology/inspection vendor base, where localization sits under 10% — so the report’s “~35% overall” tool self-sufficiency masks a category China has displaced almost nothing in (Castellano/VLSI · F120). Other analysts put KLA at 60–63 percent in 2024, including 80-plus percent of reticle inspection, around 60 percent of brightfield wafer inspection, 45 percent of CD metrology, and 40 percent of overlay metrology (Castellano · F120). Inside China the foreign hold is even tighter: the largest Chinese competitor still accounts for under 1 percent of the overall China process-control market, which makes metrology and inspection the least-localized front-end category in the country (KLA IR · F627).
Why metrology gates yield and why it is hard to copy have the same answer: the moat is software and applications, not just optics. KLA’s process-control net margin reached about 32 percent in fiscal 2023, funding a decades-deep algorithm and applications library that domestic players cannot quickly replicate (eefocus · F633; KLA IR · F627). A defect-classification engine improves with every wafer it has ever seen; a new entrant starts from zero. That is why China’s self-sufficiency in metrology sits at only 10–15 percent at mature nodes and under 5 percent for EUV-related metrology — the weakest front-end category alongside lithography (TechNews · F426; TechNews · F427). As of 2025, front-end metrology/inspection remained the single weakest equipment link in China at under 10 percent localization — the largest gap versus foreign tools (KLA, AMAT) — even as overall equipment localization reached 23.2 percent and back-end test hit ~40 percent (Electronics Weekly/Yole · F1200).
Two domestic challengers are trying to pry the gate open. Skyverse (中科飞测) is the broader optical-inspection-and-metrology player: FY2025 revenue of 2.05 billion yuan (up 49 percent), split roughly 61 percent inspection and 36 percent metrology. It only just returned to profitability — a 58.65 million yuan net profit after years of losses, earned through scale rather than margin, on the back of dark-field defect inspection and third-generation overlay metrology (xueqiu · F355; dfcfw · F345). The push remains margin-negative: Q1-2026 revenue grew 34.63 percent to 396 million yuan but the company swung back to a 68-million-yuan net loss as it lifted R&D 52.2 percent (46.26 percent of revenue) to attack the foreign monopoly — yet the order book points up, with end-Q1 contract liabilities of 881 million yuan, up 55.8 percent quarter on quarter. Its product front advanced: overlay metrology at 90nm-plus is in volume sales and 2Xnm passed top-customer line validation; dark-field nano-pattern defect inspection reached batch sales at top logic and memory customers, and bright-field inspection is shipping in batch (Sina · F1160). Dongfang Jingyuan (东方晶源, founded in 2014 by an ex-ASML employee) leads domestic e-beam inspection and CD-SEM, with commercial traction concentrated at 28nm and 14nm and a claimed first 8nm-capable CD-SEM in 2025 (Wikipedia · F275); by its 12th anniversary in February 2026 it had shipped 60-plus e-beam metrology/inspection tools (current 12-inch tools serving 28nm lines, next-generation models targeting 14nm), and covers EBI, CD-SEM, DR-SEM and HV-SEM plus computational-lithography EDA (Sina · F1173). Both are real, but together they remain inside that sub-1-percent China share — the gate is barely ajar. The chokepoint is also being reinforced from the supply side: effective 1 April 2026 the Netherlands expanded its export-control list to include specific measurement and inspection equipment from Dutch firms, requiring ASML and peers to seek Dutch-government licenses (Tom’s Hardware · F1093).
A separate strand of Chinese metrology sits outside this front-end process-control fight altogether: dimensional metrology, which measures the physical geometry of parts rather than the patterns on a wafer. The notable Xi’an player is AEH Industrial Metrology, founded in 1997 as a venture of AEH Germany and led by Dr. Jianzhong Song; it deepened its German roots by acquiring the century-old German coordinate-measuring-machine (CMM) maker MORA Metrology in 2009 (MORA · F1034). AEH builds CMMs and non-contact optical systems for semiconductor components — wafer-handling parts, ceramic suction-cup flatness, showerhead micro-holes, sputtering-target flatness, and silicon-carbide part precision (AEH · F1035; AEH · F1033). It is a genuine German-rooted, export-resilient niche supplier to the equipment and parts supply chain. But the distinction matters for the thesis: CMM metrology of physical parts does not touch the in-line wafer process metrology — critical-dimension, film, overlay, and defect inspection — that KLA dominates, so it does nothing to pry open the chokepoint above.
| Metric | Value | Source |
|---|---|---|
| KLA global process-control share (2023) | 55.8% | F633 |
| KLA global share (2024 est.) | 60–63% | F120 |
| Top-5 global concentration (2023) | over 84% | F633 |
| Largest Chinese rival, China market | under 1% | F627 |
| China metrology self-sufficiency (mature node) | 10–15% | F426 |
| China metrology self-sufficiency (advanced/EUV) | under 5% | F427 |
Back-end test — the automated test equipment (ATE) that verifies finished dies — is a softer target than metrology, and Chinese vendors have moved faster here; overall test-equipment localization reached about 40 percent in 2025 (up from 20 percent in 2020), with handlers around 60 percent (Electronics Weekly/Yole · F1200). Accotest (华峰测控) leads in analog and mixed-signal testers: FY2024 revenue of 905 million yuan (up 31 percent), net profit of 334 million yuan, and an unusually high gross margin of 73.3 percent. Domestic revenue rose 41 percent even as overseas sales fell 37 percent under trade friction, and its global installed base passed 7,500 testers by the end of 2024 (Sina · F612). FY2025 then surged: revenue 1.346 billion yuan (up 48.72 percent), net profit 536 million yuan (up 60.55 percent), installed base past 8,000 units, with its STS8600 SoC tester (benchmarked against Advantest’s 93K) completing first-CPU-customer validation and expected to ship at scale in 2026 (Yicai · F1151). Changchuan (长川科技) is the broader-line challenger: it finished 2024 with roughly 460 million yuan of net profit (Futubull · F211), then posted FY2025 revenue of 5.292 billion yuan (up 45.31 percent) and net profit of 1.331 billion yuan (up 190.42 percent), accelerating further in Q1-2026 to revenue up 69.09 percent and net profit up 217.60 percent, on domestic-substitution and OSAT capacity expansion (STCN · F1147). The higher localization in ATE reflects an easier physics problem: testers verify electrical function rather than measure sub-nanometer geometry, so the software moat is shallower.
The headline “35 percent localization” is a tool-usage figure: of the tools installed in Chinese fabs, about 35 percent were domestically made in 2025, up from 25 percent in 2024 (TrendForce · F251). That is a generous denominator. A stricter lens — vendor-revenue self-supply, or domestic vendors’ share of all equipment spending — runs much lower, around 13.6 percent overall in 2024 (TechNews · F426), and CSIS puts vendor-revenue-share metrics near 14–16 percent (CSIS · F784). The gap arises because usage counts each installed tool equally, while revenue weights by price — and the priciest tools (lithography, high-end metrology) are exactly the ones still imported. The original Made-in-China-2025 goal of 70 percent domestic equipment was badly missed; the realistic figure is 30–35 percent on the usage basis (CSIS · F784).
The tool-by-tool picture explains the average. At mature nodes (28nm and above), China is strong where it has won — photoresist strip 75–90 percent, cleaning and etch 50–60 percent — and weak where it has not: PVD 15–20 percent, CMP 15–25 percent, coat/develop 10–15 percent, ion implant 10–20 percent, metrology 10–15 percent, and KrF/i-line lithography only 10–15 percent (TechNews · F426). At advanced nodes (14nm and below) the controls bite hardest exactly where China is weakest: etch under 15 percent, CMP under 10 percent, coat/develop under 10 percent, ion implant under 5 percent, EUV-related metrology under 5 percent, and EUV or ArF-immersion exposure essentially 0–1 percent, fully import-dependent (TechNews · F427).
| Tool step | Mature node (28nm+) | Advanced node (≤14nm) |
|---|---|---|
| Photoresist strip | 75–90% | under 30% |
| Cleaning | 50–60% | n/a |
| Etch | 50–60% | under 15% |
| PVD | 15–20% | ~10% |
| CMP | 15–25% | under 10% |
| Coat/develop | 10–15% | under 10% |
| Ion implant | 10–20% | under 5% |
| Metrology | 10–15% | under 5% |
| Lithography (KrF/i-line; EUV/ArFi at advanced) | 10–15% | 0–1% |
Source: TechNews · F426; TechNews · F427. These figures come from a single Taiwan-watcher synthesis and should be read as indicative, not audited.
China became the largest single WFE market by 2024, but much of that was a one-time stockpiling spike. China’s 2024 chip capex hit about 300 billion yuan, roughly 30 percent above SEMI’s early-2024 forecast of 220 billion yuan, as fabs hoarded foreign equipment ahead of tightening export controls; domestic suppliers captured only about 60 billion yuan, or 20 percent, of those orders (Faxiangongchang · F250; 36Kr · F168). In the first half of 2024 China spent more on chipmaking tools than the US, Taiwan and Korea combined (36Kr · F168).
Figure 3 — The entire localization thesis in one ratio: China is ~40-43% of global WFE demand (the single largest destination) yet ~5% of WFE supply — an ~8x imbalance that sizes the captive home market domestic vendors are growing into. Source: Yole · F597; SEMI WFE total · F1263; self-supply <14% · F600.
The clearest read on China’s WFE weight, and on its decline, comes from the foreign tool makers’ own filings. ASML reported that China was 41 percent of its FY2024 net system sales by ship-to location — its single largest region, up sharply from 29 percent in 2023. That demand weight is the mirror image of China’s supply weight: China is ~40-43% of global WFE demand (~$49B of a ~$116B market) but only ~5% of WFE manufactured anywhere — an ~8x demand-over-supply imbalance that defines the captive home market domestic vendors are growing into (Yole · F597; SEMI · F1263). ASML called it a stockpiling-driven peak, after which it guided China down to roughly 20 percent of total net sales in 2025 (ASML 6-K · F945). KLA tells the same story: China was about 43 percent of its fiscal-2024 revenue and fell to about 33 percent in fiscal 2025 as export restrictions tightened, though it remains KLA’s largest single geography (KLA IR · F627; Castellano · F122). The market-level data confirms the trend: Gartner’s 3Q25 read puts China’s WFE share falling to about 31 percent (from 36 percent in 2024), and SEMI — even while keeping China the top equipment-spending destination on its 2025–2027 forecast (global WFE 115.7 billion USD in 2025, +9 percent in 2026) — now expects China sales to gradually decline from 2026 (SEMI · F1144). The fall in China’s share of these vendors’ revenue captures two forces at once — the unwinding of the 2024 stockpile and the controls cutting off advanced-tool sales — and signals that the import binge has peaked.
Even so, domestic equipment investment kept growing counter-cyclically. In H1 2025, total semiconductor investment in greater China fell 9.8 percent to 455 billion yuan, yet equipment investment rose 53.4 percent — the only segment with positive growth — and domestic equipment order value surged about 80 percent (Faxiangongchang · F253; 36Kr · F168). China’s overall wafer capacity rose about 15 percent to 8.85 million wafers per month in 2024 and a further 14 percent to roughly 10.1 million in 2025 — nearly a third of global capacity, with more added in 2024 than the rest of the world combined; WFE spend rose from 11 billion USD in 2018 to nearly 30 billion USD in 2023 (TechInsights · F695). The May 2024 Big Fund Phase III, about 48 billion USD on top of cumulative state funding above 150 billion USD, is financing the substitution (TechInsights · F695).
The localization wins carry a financial catch: revenue is racing ahead of profit. The starkest cases sit at the edges of the equipment roster. Kingsemi grew FY2025 revenue 11 percent to 1.95 billion yuan but saw net profit collapse 65 percent to 72 million yuan — and in H1 2025 net profit fell 79 percent — as staff costs rose, government subsidies shrank, and asset impairments mounted; Q1-2026 continued the “revenue up, profit not” squeeze with rising inventory (Sina · F428; Stockstar · F1143). Skyverse, the metrology challenger, grew FY2025 revenue 49 percent yet earned only 58.65 million yuan of net profit, having only just escaped losses — and slipped back to a 68-million-yuan net loss in Q1-2026 as R&D spending jumped 52 percent to break the foreign monopoly (xueqiu · F355; Sina · F1160). Even NAURA, the strongest, closed FY2025 with net profit down 1.77 percent — its first profit dip — against 31 percent revenue growth, as R&D rose 34.74 percent (增收不增利, “revenue grows but profit doesn’t”) (Sina · F1089).
The pattern reflects margin compression from a price war for domestic share, heavy R&D loads (AMEC at 31 percent of revenue, Hwatsing’s R&D up 40 percent), and the loss of subsidy support as programs mature (TrendForce · F277; Sina · F393). The exceptions prove the rule: the firms with durable margins are the ones in the least-contested niches — Accotest at 73 percent gross margin in analog ATE, and ACM’s electroplating and furnace segment at about 60 percent gross margin (Sina · F612; SSE · F375). Where competition is fiercest, growth is buying share, not profit.
China’s headline localization numbers flatter its progress. The country has built credible domestic suppliers across nearly every chip-making consumable: photoresist, polishing slurry, specialty gases, silicon wafers, sputtering targets, packaging film. But beneath almost every input China has localized sits a deeper one that remains foreign-monopolized — the monomer beneath the resin beneath the resist, the abrasive beneath the slurry, the silica filler beneath the build-up film, the quartz mineral beneath the synthetic glass. Call it the localization of the localization: a 40 percent self-sufficiency figure for one layer can rest on a 1 percent figure for the layer below. The same map runs in reverse on a short list of inputs where China, not the West, holds the monopoly — gallium, germanium, antimony, tungsten, and rare earths. There China owns the floor of the stack, and in 2025 it spent that leverage to win back access to chip-design software. This section maps both halves: how shallow most of China’s materials localization is, and how real the one weapon it holds turns out to be.
Figure 1 — The asymmetry in one view: China’s photoresist
self-sufficiency collapses to near-zero at the high end (left), even as
it controls the global supply of the minerals the world depends on
(right). Early-2026 data confirms the high-end gap held — KrF still ~5%,
combined KrF+ArF <1%, EUV resist R&D-stage — even as the overall
2026 self-sufficiency target is 40%. Source: SDIC Securities ·
F409; TrendForce
· F1057; USGS/CSIS ·
F717.
Photoresist — the light-sensitive coating that records a circuit pattern when a wafer is exposed — is the clearest Japanese chokepoint. Japan controls more than 70 percent of the global photoresist market and roughly 95 percent of high-end extreme-ultraviolet (EUV) resists, with Shin-Etsu Chemical and Tokyo Ohka Kogyo (TOK) together holding about 80 percent of the world market (TrendForce · F81). Independent 2024 market research confirms the concentration: the top three Japanese suppliers (TOK, JSR and Shin-Etsu) hold more than 90 percent of the EUV-resist market, with JSR alone above 22 percent; in deep-ultraviolet (DUV) resists, four Japanese firms (JSR, TOK, Shin-Etsu and Fujifilm) hold a combined ~72.5 percent and lead the argon-fluoride (ArF) immersion chemistry used at advanced nodes, through long foundry relationships with Intel, Samsung and TSMC (Mordor Intelligence · F715).
China’s domestic layer is genuinely thin. Overall photoresist localization was only about 10 percent in 2024, against a national target of 40 percent self-sufficiency by 2026; high-end resists were under 5 percent locally produced as of 2022, and krypton-fluoride (KrF) DUV resist met only about 5 percent of domestic demand (TrendForce · F80). By early 2026 the high-end gap had not closed: China still met only ~5 percent of its KrF demand (110–180nm) and remained almost entirely dependent on Japan for ArF DUV (7–65nm), with its combined KrF+ArF share still below 1 percent and EUV resist stuck at the R&D stage; the >20 percent self-sufficiency it has reached is confined to older g/i-line resists for power and LED chips (TrendForce · F1057). The squeeze is also weather-dependent: a magnitude-7.3 Fukushima-area earthquake in February 2026 disrupted Shin-Etsu capacity and prompted fresh rumored Japanese KrF supply curbs, pulling forward mainland KrF qualification (TrendForce · F1057; Digitimes · F1069). The domestic suppliers that exist are real but small.
| Firm | Resist type | Status (2024–25) | Source |
|---|---|---|---|
| Nata / Nanda Optoelectronic (南大光电) | ArF (dry + immersion), EUV pilot | Fastest-moving mainland ArF player; dry-ArF passed multi-process validation and entered small-batch supply, qualified at one memory + one logic fab for 90–14nm; built China’s first 25-ton ArF line (a ~500t figure is planned design capacity, not shipment); only firm to pass the national 02-project EUV-resist R&D milestone, now building a ~50-ton EUV pilot (中试) line | STCN · F344; Tencent · F1068 |
| Tongcheng / Beijing Kehua (彤程新材/北京科华) | KrF (sole volume domestic supplier), ArF | China’s effectively sole volume KrF (248nm) supplier, covering SMIC, CR Micro, Silan, Sanan etc.; by early 2026 its ArF resist had reached mass production while KrF qualification is being accelerated into more fabs; the 2026 Shin-Etsu KrF crunch is pulling its qualification forward | East Money · F500; Digitimes · F1069 |
| Dinglong (鼎龙股份) | ArF, KrF | Passed customer evaluation, orders from two domestic fabs; designs own monomer/resin/PAG for full-chain localization | Tom’s Hardware · F198 |
| Jingrui (晶瑞电材) | KrF (customer-testing), ArF in R&D | KrF resolution 0.25–0.13μm; g/i-line ships to SMIC, CXMT, Hua Hong, Nexchip; completed KrF pilot and entered the customer-testing stage by early 2026, with ArF still in R&D | Tencent Finance · F625; Tencent · F1168 |
| Shanghai Sinyang (上海新阳) | ArF-immersion (first order), KrF | KrF in batch sales; ArF-immersion got first sales order in 2025; dry-ArF entered capacity-construction stage by early 2026; total photoresist sales grew >100% YoY in 2024 — second tier behind Nanda (validated) and Tongcheng (ArF mass-produced) | CLS · F718; Metal.com · F1157 |
The leverage is not hypothetical. In November 2025 Japan’s Ministry of Economy, Trade and Industry (METI) placed 12 core semiconductor materials, including high-end ArF and EUV photoresists, on its export control list, restricting supply to 42 Chinese companies; reports say Shin-Etsu, TOK, JSR and Fujifilm then suspended ArF-immersion and EUV deliveries to mainland customers (Asia Times · F91). No Chinese firm holds any qualified EUV resist at all. The next-generation EUV chemistry is moving toward tin-oxide metal-oxide resist (MOR), whose pioneer Inpria was bought by Japan’s JSR in 2021 for about USD514M — leaving only three qualified volume EUV-resist suppliers worldwide (TOK, JSR, Shin-Etsu), all Japanese-owned (JSR · F1001). China is beginning to scaffold a domestic EUV-resist push — it filed its first national EUV-resist standard (EUV Photoresist Test Methods, 极紫外光刻胶测试方法) in October 2025, and Nanda is building a ~50-ton EUV pilot line as the only firm past the 02-project EUV milestone — but mass production remains years away (Tencent · F1168; Tencent · F1068).
Even where China has localized the finished resist, the gate has simply moved upstream. A finished resist is built from a resin, a photo-acid generator (PAG), an electronic-grade solvent and additives — and beneath the resin sits the monomer. Japan’s dominance rests on owning this whole finely divided chain, with separate firms for monomer, resin, additive and resist. For China, the monomer and post-processing are the binding constraints: ArF/KrF resist localization measured at the raw-material level is reportedly only around 1 percent, though some sources put KrF at 5–10 percent (Guancha · F709).
Two sub-components below the monomer/resin layer are the tightest of all. The photo-acid generator — the molecule that triggers the chemical reaction on exposure — is the most concentrated chokepoint in photoresist: the global top four (Japan’s Toyo Gosei and San-Apro, Fujifilm Wako, plus Heraeus) hold over 90 percent of the market, and high-end advanced-node PAG remains Japan-dominated even as China’s Changzhou Tronly emerges (QYResearch · F853). The workhorse solvent, electronic-grade PGMEA, makes up more than 80 percent of the resist formulation by content and is the most localizable input — China has expanded PGMEA capacity past 400,000 tons. The ranking of difficulty, then, runs PAG hardest, monomer next, solvent most localizable (QYResearch · F853).
China’s most credible answer is Xuzhou Boron (徐州博康), 26.21 percent owned by Huamao Technology with Huawei’s Hubble fund as third-largest shareholder. It is the only mainland photoresist firm with a fully self-supplied upstream — monomer, resin, PAG and finished resist — and is itself a stable monomer supplier to JSR, Dow, Sumitomo and Intel. By end-2022 it had reserved about 80 percent of global photoresist-monomer technology and held more than 20 percent of the global KrF-monomer share (DRAMeXchange · F712). That single firm is the exception that proves the rule: full-chain localization in resist is rare, and the high-end resist’s roughly six-month shelf life means stockpiling cannot substitute for it for long (Guancha · F709). In March 2026, Xuzhou Boron’s chairman Fu Zhiwei said its mid-to-high-end KrF and ArF products had already passed verification at leading foundries and were beginning to scale, with the firm aiming to mass-produce several core advanced-node resist materials within five years (TrendForce · F1081).
The resist story repeats across every other localized consumable.
Figure 2 — The localization of the localization: every input China
has localized rests on a deeper foreign-monopolized one, and all four
chains share a single US/European mineral floor. EUV mask has no
China-localized layer at all. Source: Pengyuan
· F667; QYResearch
· F853; TechNews ·
F502; SemiconSam
· F1015; Lianrui
prospectus · F834; Veeco
· F875; Sibelco
· F993.
CMP slurry. Chemical-mechanical planarization (CMP) — the polishing step that flattens each wafer layer — depends on slurry (about 49 percent of CMP-consumable value) and pads (about 33 percent). Foreign firms hold more than 80 percent of China slurry demand and over 90 percent of the high-end global market, with US Cabot/CMC (now Entegris) long holding ~64 percent of the China market; pads are even more concentrated, with DuPont at ~75–79 percent globally and Dinglong the only mainland firm able to mass-produce them (Sina/Guojin · F666). The deeper chokepoint sits upstream of even the localized slurry: the abrasive particle. Silica abrasive — about 70 percent of slurry abrasive — is dominated by Japan’s Nissan Chemical and Fuso Chemical plus AkzoNobel, while cerium-oxide abrasive is monopolized by Belgium’s Solvay (Pengyuan · F667). China’s slurry leaders have localized the formulation but remain exposed at the abrasive layer; the silica-abrasive market further splits into colloidal and fumed grades held by Fuso, Merck, Nouryon, Grace and Evonik, and in 2023 Fujifilm’s acquisition of Entegris’ slurry business made it the world’s largest CMP-slurry supplier (Valuates · F835). The 2026 split crystallizes the pattern: slurry is the most-advanced CMP localization, with domestic leader Anji Microelectronics (安集科技) forecasting revenue rising from RMB2.47B (2025) to RMB3.18B (2026) at ~57–58 percent gross margins — yet Anji still imports its key abrasives (silica sol, fumed silica) from Japan’s Fujimi and US Cabot, exactly the upstream gate described above. Pads lag far behind, with domestic output meeting under 30 percent of Chinese demand in 2026 (projected only 40–45 percent by 2035) and Dinglong the lead supplier, qualified at fabs including YMTC for mature-node (28nm and above) oxide/W CMP; China is about 18 percent of the ~USD2.8B 2026 global CMP-slurry market (Reportify/industry · F1099).
ABF and FC-BGA substrates. Ajinomoto Build-up Film (ABF) — the insulating resin, derived from a monosodium-glutamate byproduct, that is the de facto standard dielectric for CPU/GPU flip-chip packaging — is held more than 95 percent by Ajinomoto (estimates range up to ~99 percent) (Convergence Analysis · F169; Sina · F697). China’s ABF-substrate localization rate was just ~4 percent in 2024, projected ~5 percent in 2025, with the four mainland substrate makers (Shennan, AT&S-linked, Access/Yueya, Xingsen) together holding only ~6 percent of the market (fsemi · F698). Below the ABF film itself sits another import: the Japanese silica micro-powder (silica filler) that sets the resin’s thermal-expansion and dielectric properties, on which high-end demand depends (fsemi · F698). Mainland firms hold only ~3.2 percent of the global IC-substrate market against Taiwan’s big three (Unimicron, Nan Ya, Kinsus) at ~40 percent, and the build-up film is almost entirely Japan-sourced from Ajinomoto (one Taiwanese reading puts it near 99 percent, the top of the estimate range above) (TechNews · F502). The squeeze is tightening, and AI demand has now made ABF the next supply bottleneck after wafers and HBM: foreign brokers raised the projected 2030 ABF-substrate supply gap from 15 percent to 22 percent (TechNews · F423). By mid-2026 a US-bank read put the shortfall at ~10 percent in H2-2026, widening to ~21 percent in 2027 and ~42 percent by 2028, as AI chips climb from ~10 percent to ~75 percent of ABF demand by 2030; Ajinomoto (Fine-Techno), holding ~95 percent of CPU/GPU-grade film, announced a ~30 percent price hike effective Q3-2026 (Digitimes · F1098). China’s champions are scaling the substrate layer beneath that film: Shennan Circuits now has volume capability for 14-layer-and-below FC-BGA (developing 20-layer) and Xingsen/Fastprint has 20-layer-and-below capability with >20-layer in test, while Shenzhen Newfeics is developing a domestic ABF-film substitute — but the film itself remains Ajinomoto’s (Digitimes · F1098).
Photomask blanks and substrates. Below the photomask blank — a Hoya/AGC duopoly — sits the ultra-flat, low-thermal-expansion synthetic fused-silica substrate the blank is built on. That layer is an oligopoly of Heraeus, Shin-Etsu Quartz, AGC, Corning and Tosoh, holding an estimated 80–85 percent of premium-grade fused-silica shipments into Asia in 2025, and China has no qualified domestic supplier of mask-grade synthetic fused-silica substrate at advanced nodes (Valuates · F722). The mask’s own recording chemistry — the e-beam chemically-amplified resist coated on the blank — is also Japan-led (JSR, TOK): yet another mask sub-input where China has no qualified advanced material (SemiEngineering · F898).
The mineral floor. At the literal bottom of this stack is natural high-purity quartz, roughly 70–90 percent of which comes from two mines in Spruce Pine, North Carolina (operated by Sibelco and The Quartz Corp); together they account for more than 80 percent of global commercial supply. China produces only about 5,000 tons a year and cannot yet match Spruce Pine grade (Sibelco/BloombergNEF · F993). Even China’s localized synthetic-quartz and wafer chains rest on this US/European-controlled mineral floor — and semiconductor-grade quartz localization in China is itself under 10 percent, with leader Feilihua’s high-purity synthetic-quartz-sand project still only at pilot phase (Feilihua · F800).
The picture is not uniformly bleak. In three materials categories, Chinese firms have reached global leadership or near-leadership — and these are the data points that headline localization figures lean on.
Specialty gases. CSSC Pairui Special Gas (中船特气), spun out of a state shipbuilding research institute, holds the world’s largest capacity in two core electronic gases: 18,500 tons/year of ultra-high-purity nitrogen trifluoride (NF3, ranked #1 globally) and 2,000 tons/year of tungsten hexafluoride (WF6, also #1, ahead of Japanese and Korean makers). Its 6N-purity WF6 meets 3D NAND, HBM and advanced-logic needs, with customers including TSMC, Micron, SK Hynix, SMIC and CXMT (CSSC · F408). Huate Gas (华特气体) is the only mainland gas firm whose excimer-laser lithography mix-gases are certified by both ASML and Gigaphoton; it has achieved import substitution for 55+ products, with 20+ supplying 14nm and 7nm lines and some reaching 5nm, and it covers more than 90 percent of mainland 8–12 inch fabs plus Samsung, SK Hynix and TSMC (Huate · F690; Huate · F541). The caveat: foreign giants (Linde, Air Liquide, Nippon Sanso) still control about 88 percent of the China electronic specialty-gas market, Huate’s own share is under 5 percent, and China can produce fewer than 30 percent of the gas varieties used in IC production (Huate · F133). Per the China Industrial Gas Association, only about 20 percent of electronic specialty-gas varieties for IC production can currently be made domestically (global top-10 hold >90 percent of the ~RMB23B 2024 market), but select gases — NF3, CF4, SF6, WF6, N2O and ammonia — are partly past 50 percent localization (industry · F1114). The WF6 squeeze is now playing in CSSC Pairui’s favor: in early 2026 Japan’s Kanto Denka and Central Glass warned Korean customers including Samsung that WF6 raw-material inventory would last only to late May/June 2026 with uncertain H2 supply, handing share to Chinese makers (industry · F1114).
Silicon wafers. The top seven domestic wafer makers commanded about 86 percent of China-produced (localized) wafer volume in 2024, with National Silicon Industry Group (NSIG) in the vanguard (Tom’s Hardware · F73). NSIG reached about 370,000 300mm-wafers/month by mid-2023 and targets eventual expansion to 1.2 million (Tom’s Hardware · F65). Chinese makers’ global share of 12-inch wafer capacity jumped from 3 percent in 2020 to 28 percent in 2025 and is expected to reach 32 percent in 2026, led by ESWIN Materials, against an unwritten ~70 percent domestic-procurement target judged likely to be met (TechNews · F532). ESWIN is funding the run-up via a STAR Market IPO to lift output from 650,000 to 1.2 million 12-inch wafers/month — roughly 40 percent of Chinese demand and a >10 percent global share — and NSIG reported FY2025 revenue growth on higher 300mm shipments (margins pressured by pricing); the global top-five still hold ~80 percent of 12-inch capacity, and leading-edge quality still leans on the foreign incumbents (Digitimes · F1082).
Sputtering targets. Jiangfeng Electronic (江丰电子) — founded by an ex-Honeywell engineer — broke the Japan/US oligopoly in ultra-high-purity aluminum, titanium, tantalum and copper targets. By 2025 its global semiconductor-target share reached about 22 percent, ranking #2 worldwide behind only JX Nippon Mining, and by end-2024 it ranked #1 globally in semiconductor-target shipment volume, supplying SMIC, TSMC, SK Hynix and BOE (Dongfang/Securities · F660). The global sputtering-target market was about USD13B against a domestic market of about USD5B, leaving substantial substitution headroom (Yunch · F170).
Even here, the upstream gate recurs. ALD/CVD deposition precursors — the chemistries fed into thin-film deposition tools — are only about 40 percent localized in China, with the global market led by Germany’s Merck (~33 percent) and France’s Air Liquide (~30 percent), and the three foreign majors holding ~76 percent of the China market specifically (Tencent · F705). The lesson holds across the board: China’s strongest materials wins are real, but they sit alongside layers that remain firmly foreign.
The mirror image of the import-dependence map is the short list of inputs where China owns the monopoly — and this leverage is genuine, not shallow. Per USGS 2023 production data and think-tank readings, China produces roughly 98 percent of the world’s low-purity gallium, about 68 percent of refined germanium, and around 48 percent of mined antimony; the International Energy Agency finds China the dominant refiner for 19 of 20 analyzed minerals, averaging about 70 percent share (USGS/CSIS · F717). On a refined-product basis the concentration is starker still: by late-2025/2026 readings China held about 99 percent of refined gallium, roughly 60–83 percent of germanium, and about half of mined antimony — the leverage is intact even as it is, for now, only paused (Fastmarkets · F1041). This position was built deliberately: China exploited a 2012–2017 gallium surplus and used subsidies to push German and Kazakh producers into closure. Because many of these metals are byproducts (gallium from aluminum, germanium from zinc), supply is slow to replace; USGS estimated a gallium/germanium ban alone could cost the US economy about USD3.4B, roughly half from semiconductors (USGS/CSIS · F717).
China escalated the use of this leverage in deliberate, US-mirroring steps.
| Date | Measure | Source |
|---|---|---|
| Aug 2023 | Export licensing on gallium and germanium | Mayer Brown · F112 |
| Sep 2024 | Export licensing on antimony | Mayer Brown · F112 |
| 3 Dec 2024 | Outright presumption-of-denial on Ga/Ge/Sb/superhard exports to the US (MOFCOM No.46), issued one day after the US added 140 entities | CSET translation · F609 |
| 4 Feb 2025 | Added tungsten, tellurium, bismuth, molybdenum, indium (No.10) | ESM China · F453 |
| 4 Apr 2025 | Controls on seven medium/heavy rare earths (samarium, gadolinium, terbium, dysprosium, lutetium, scandium, yttrium) under No.18 | MOFCOM · F604 |
| 9 Oct 2025 | Sweeping extraterritorial rare-earth regime (No.61/62): China’s first-ever 0.1% de-minimis rule, a Foreign Direct Product Rule, and a 50% presumptive-denial rule mirroring the US BIS Affiliates Rule | CSET · F1155 |
| 1 Nov 2025 | Busan Trump-Xi truce: one-year mutual suspension — China suspends No.61/62 (via No.70, 7 Nov) and No.46 Article 2 Ga/Ge/Sb (via No.72, 9 Nov, to 27 Nov 2026); US suspends its 50% Affiliates Rule | CNBC · F1044 |
| 22 Jun 2026 | Added 10 US firms — incl. rare-earth champions MP Materials and USA Rare Earth — to the export-control list (full transfer ban), retaliating for the US 1260H military-linked list update | Al Jazeera · F1049 |
The controls bit. After August 2023 licensing, Chinese gallium exports fell from 6,876 kg in July 2023 to 227 kg by October, and germanium from 7,965 kg to 590 kg; gallium prices rose about 18 percent in China and ~68 percent in Europe (Stimson · F113). In the year after the December 2024 curbs, Chinese press reported germanium ingot up 64.2 percent, gallium up 53.4 percent, and antimony up 212 percent, with antimony exports plunging about 97 percent month-on-month in October 2024 (ThePaper · F434). Germanium ran from about USD1,500/kg in June 2023 to roughly USD6,200–6,300/kg by March 2026 — more than a fourfold gain — and the US is highly exposed, having drawn 54 percent of its germanium and 53 percent of its gallium imports from China over 2018–2021 (OFweek · F464). Independent quantification confirms the bite: USITC analysis of Chinese customs data found wrought-germanium average export unit value up 56 percent comparing pre- and post-control periods, European germanium spot prices up ~400 percent, and global antimony-trioxide prices roughly tripling, even as USGS estimated a full Ga/Ge ban could lift gallium prices ~150 percent (USITC · F1056). The MOFCOM No.46 structure is worth precision: Article 1 imposes a blanket ban on dual-use exports to US military end-users, while Article 2 set the Ga/Ge/Sb presumption of denial. This whole architecture became the central bargaining chip of the late-2025/2026 talks. The October 2025 extraterritorial rare-earth regime forced the US to the table; at the 30 October–1 November 2025 Busan summit, Trump and Xi struck a one-year truce in which China’s critical-minerals leverage was the central concession, and on 9 November 2025 MOFCOM No.72 suspended Article 2 until 27 November 2026 (alongside the 7 November suspension of the Oct-2025 rare-earth controls), reverting Ga/Ge/Sb to ordinary licensing — but the Article 1 military-end-user ban remains in full force (CSET translation · F609; CNBC · F1044). Critically, the framework is paused, not removed: the metals stay on the dual-use list, the suspension is reversible and expires 27 November 2026, and Beijing kept adding targeted controls through 2026 (the 22 June listing of MP Materials and USA Rare Earth), so analysts advise pricing for optionality, not certainty (USITC · F1056; foreign policy synthesis · F1169).
The clearest proof that China’s materials leverage is real came in mid-2025, when Beijing traded it directly for chip-design software. In late May 2025, the US Bureau of Industry and Security (BIS) restricted exports of electronic design automation (EDA) tools — the software from Synopsys, Cadence and Siemens that no chip can be designed without — to China. On 2 July 2025, BIS rescinded those restrictions effective immediately, roughly six weeks after they took effect, as part of a broader US-China trade truce explicitly tied to China resuming rare-earth exports; all three EDA vendors confirmed receipt of rescission letters (CNBC · F6). Analysts read the episode as a map of where the leverage lies: the EDA cutoff lasted about six weeks and was traded for rare earths, showing the US treated EDA as the more negotiable lever, while allied lithography controls remained durably in place (CSIS · F271).
China’s broader rare-earth position is what made the card playable. Its April 2025 controls reached the magnet-critical heavy rare earths — terbium, dysprosium, samarium — that are hardest to substitute, covering not just metals and oxides but semi-finished neodymium-iron-boron and samarium-cobalt magnet blanks; China controls roughly 90 percent of global rare-earth separation capacity (MOFCOM · F604). The leverage is now extending into the tungsten/WF6 chain that feeds semiconductor deposition: by early April 2026, the main global WF6 producers, Japan’s Kanto Denka and Central Glass, warned Korean customers including Samsung that raw-material inventories would last only to late May or June, after MOFCOM tightened tungsten controls toward Japan in January 2026 — positioning China’s WF6 leader CSSC Pairui to gain share as Japanese feedstock tightens (CNFIN · F469). One input runs the other way: hafnium, the core high-k precursor metal, is the rare semiconductor material where China is not the chokepoint — it produces hafnium for its own demand while the West sources from France, the US and Australia (SemiconductorInsight · F849). As of mid-2026 the truce that freed the rare-earth card still held — a senior US official confirmed it remained in effect and could be extended — but with the strictest rules under a partial suspension expiring around 10–27 November 2026, rare earths remain China’s most potent trade-war tool and both sides continue jockeying for leverage as the fall-2026 expiry approaches (Foreign Policy · F1115).
Headline localization rates overstate real self-sufficiency. A “40 percent” figure for one layer routinely rests on single-digit self-sufficiency in the layer beneath it — resist localization at ~10 percent overall masks ~1 percent localization of the upstream monomer/PAG (TrendForce · F80; Guancha · F709). The 2026 target year has not closed the gap: by early 2026 China still met only ~5 percent of KrF demand, its combined KrF+ArF share stayed below 1 percent, and EUV resist remained R&D-stage (TrendForce · F1057). The capability story is shallower than the investment story implies.
The chokepoint moves upstream; it does not disappear. Every consumable China has localized — slurry, ABF, masks, wafers — has a foreign-monopolized input one layer down: Solvay ceria, Ajinomoto film, Heraeus/Shin-Etsu fused silica, Spruce Pine quartz (Pengyuan · F667; Sibelco · F993). Localization is a layered race, not a one-time achievement.
A few domestic suppliers are genuinely world-class — and worth funding. CSSC Pairui (#1 in NF3 and WF6), Jiangfeng (#2 in semiconductor targets), Huate (dual ASML/Gigaphoton certification), and the wafer makers show that targeted capital plus procurement mandates can produce real global leaders, validating the investment thesis where it is concentrated (CSSC · F408; Dongfang · F660).
China’s materials weapon is real, and it has been fired — and only holstered. Gallium ~98 percent (≈99 percent of refined), germanium ~68 percent, antimony ~48 percent, rare-earth separation ~90 percent — and the price moves after each control (germanium spot up ~400 percent in Europe, antimony trioxide tripling) prove the leverage is not theoretical (USGS/CSIS · F717; USITC · F1056). The Ga/Ge/Sb ban is merely suspended under the Busan truce to 27 November 2026, the framework intact and reversible — making the late-2026 expiry a live risk window the West cannot ignore (Fastmarkets · F1041; Foreign Policy · F1169).
The rare-earth card already bought a US concession. The six-week EDA cutoff, traded back for rare earths, is the cleanest evidence that materials leverage converts into negotiating power over the technology layer (CNBC · F6; CSIS · F271).
Net: capability is overstated, but the counter-leverage is underestimated. China cannot yet supply its own deepest inputs, yet it controls the West’s — an asymmetry that makes the sub-tier both China’s greatest remaining vulnerability and its sharpest weapon.
Most of this report tracks where China is losing or stuck: leading-edge logic, EUV lithography, HBM. This document is the inverse. In four device families China is not catching up but already leading or co-leading global share — power chips built on silicon carbide (SiC), power chips built on gallium nitride (GaN), CMOS image sensors (CIS), and outsourced advanced packaging. One structural fact ties them together: none needs extreme-ultraviolet (EUV) lithography or leading-edge (7nm-and-below) transistors, so none sits inside the export-control regime that throttles China’s AI-logic ambitions. China competes here on capacity, cost, and a captive domestic demand pull, and it is winning on volume and share. The catch shows up in nearly every champion’s financials: the same price aggression that captured share has gutted near-term profit. This is a deliberate share-now, margin-later land grab in the corners of the industry that sanctions cannot reach.
Figure 1 — In three families that need no EUV or leading-edge
lithography, a Chinese firm is already the single global #1. Source: TrendForce
· F927, Stockstar ·
F902, CMBI
· F885.
Wide-bandgap power devices — SiC and GaN — are made on mature 200mm (8-inch) lines and need no EUV or leading-edge lithography, so they fall largely outside the controls that target advanced compute. Omdia notes that compound semiconductors sit at the center of China’s 14th Five-Year Plan precisely as a self-reliance and sanctions-circumvention play (Omdia · F1010). Image sensors follow the same logic: CIS are built on trailing-edge nodes — roughly 22nm to 180nm, with the pixel array commonly at 55nm/65nm class and stacked logic at 28-40nm — well above the FinFET and EUV thresholds the controls touch, so Chinese foundries face no equipment barrier to CIS-class processes (Yole · F872). Advanced packaging is an assembly-and-interconnect discipline, not a transistor-shrink one; its constraints are interposers, bumps, and substrates, not lithography generations.
The consequence is that the contest moves onshore, on China’s cost terms. Western incumbents respond by localizing rather than exiting. onsemi set up a Greater China headquarters in Shanghai in March 2026, targeting roughly 50% localized bill-of-materials across three factories — up from low single digits five years earlier — and signed an MOU with Innoscience to source GaN on Innoscience’s 200mm GaN-on-silicon process. A US power leader is now buying GaN from China’s champion (TrendForce · F1009).
SiC substrates are the wafers that SiC power chips are built on. China’s land grab here is the clearest single offense in the report, and the most self-inflicting.
The share win is decisive, though how decisive depends on the lens. SICC (Shandong Tianyue, 688234.SS / 2631.HK) became the global #1 conductive-SiC-substrate maker in 2025, taking 27.6% of the conductive-SiC market and 51.3% of the 8-inch segment, with every rival under 15% on 8-inch (Stockstar · F902). On TrendForce’s narrower 2024 N-type revenue ranking the Chinese ascent reads as a one-two-three: Wolfspeed still led at 33.7%, but TanKeBlue (17.3%) and SICC (17.1%) took #2 and #3 ahead of Coherent (13.9%), the top four controlling 82% — and the China share has only climbed since, as SICC’s 2025 #1 claim and Wolfspeed’s bankruptcy attest (TrendForce · F1178). To put that in Western scale terms: TanKeBlue and SICC combined (~34% of 2024 N-type revenue) now roughly equal Wolfspeed, the US firm that pioneered and long dominated the market — and Wolfspeed filed Chapter 11 on 30 June 2025, explicitly citing Chinese pricing, after 6-inch wafer prices collapsed from ~US$1,500 (2022) to under US$400 (2025-26) (TrendForce N-type · F749; price war · F1148). TanKeBlue, the largest domestic supplier for China’s power-electronics market, passed one million cumulative substrate shipments in early 2025 (TanKeBlue · F995). Upstream, Yole estimates Chinese players already held about 40% of global SiC wafer/epiwafer capacity in 2024 and over 30% of SiC materials market share (Yole · F912).
Figure — The clearest ‘China displaces the West’ casualty: two
Chinese makers combined (~34%) now roughly equal once-dominant
Wolfspeed, which filed Chapter 11 (30 Jun 2025) citing Chinese pricing
after 6-inch wafer prices fell from ~$1,500 (2022) to <$400
(2025-26). Source: TrendForce
N-type ranking · F749; SICC
#1 2025 · F737; price
war · F1148.
Seen across one year rather than as a single snapshot, the displacement is starker still. In the 2024 N-type ranking SICC sat third; by 2025 it was the global #1 — and the firm it displaced, Wolfspeed, was in Chapter 11 in the very same frame.
Figure — SiC substrate leadership flipped from Wolfspeed to China in
one year: SICC went from #3 (2024, 17.1% N-type) to global #1 (2025,
51.3% of 8-inch) while the ex-leader Wolfspeed filed Chapter 11 (30 Jun
2025), the casualty in the same frame. Columns use different segment
bases (2024 full N-type revenue vs 2025 8-inch), so the flip is real but
not a like-for-like stack. Source: TrendForce
2024 N-type ranking · F1178, F749;
SICC
#1 2025 · F737; Wolfspeed
Chapter 11 + price collapse · F1270.
The price war is the cost, and China triggered it. After a 2019-2024 capex boom, the power-SiC industry tipped into a correction: by 2025 utilization had fallen to roughly 50% upstream (crystal/wafer) and 70% on device lines, and the downturn is expected to persist into 2027-2028 (Yole · F912). By 2026 the war had migrated down a wafer size: it is now centered on 6-inch conductive substrates, where mainstream quotes have fallen below US$500/wafer and into the US$400-or-lower range, with some suppliers pricing near cost — while the industry races to 8-inch, which cuts unit cost roughly 35% and is forecast to climb from under 2% of products to about 15% of shipments in 2026 and over 20% by 2030, displacing 6-inch over 2026-2027 (TrendForce · F1148). A late-2025 twist squeezed makers from both ends: low-end bulk SiC raw-material prices rose on runaway production costs even as 6-inch substrate prices kept plunging on oversupply (TrendForce · F1197). A new demand vector also opened — SiC as a thermal-management material for AI/HPC GPUs (thermal conductivity up to 500 W/mK), with Wolfspeed producing a single-crystal 300mm SiC wafer in January 2026 for AI infrastructure and AR/VR (TrendForce · F1148). The Chinese overbuild is the structural driver, and the casualties are mostly non-Chinese.
| Company | Status | What happened |
|---|---|---|
| Wolfspeed (US, ex-#1) | Chapter 11, Jun-Sep 2025; first post-emergence quarters still loss-making | Prepackaged bankruptcy filed 30 Jun 2025, emerged 29 Sep 2025; shed ~70% of debt (~US$4.6B); explicitly cited aggressive Chinese SiC pricing (Financier Worldwide · F889). Its first full post-emergence quarter (Q2-FY2026, ended 28 Dec 2025) posted revenue ~US$168M at a GAAP gross margin of -46%; Q3-FY2026 (ended Mar 2026) was US$150.2M at -27% GAAP GM — still negative on underutilization and customer second-sourcing during the bankruptcy, though AI-datacenter revenue grew +50% sequentially (Wolfspeed Q2-FY2026 · F1110) |
| Renesas (Japan) | Exited SiC-for-EV | Converted its US$2.1B Wolfspeed wafer-supply deposit to equity/notes, then quit SiC power for EVs, blaming rising Chinese output (Financier Worldwide · F889) |
| JS Foundry (Japan) | Bankruptcy, Jul 2025 | Filed for bankruptcy July 2025 amid the same downturn (Yole · F912) |
| STMicroelectronics | Targets pushed out | FY2025 net profit fell to US$299M from US$1.99B; pushed its US$20B revenue target from 2027 to 2030 (SEC 6-K · F913) |
| SICC (China, new #1) | Net loss | Swung to a FY2025 net loss of -RMB208M despite shipping more volume (Stockstar · F902) |
The last row is the irony. The same price aggression that gutted Wolfspeed also pushed China’s own leader into the red. SICC’s FY2025 revenue fell 17.15% to RMB1.465B even as substrate volume rose; gross margin collapsed to 13.05% from about 26%, and the company swung to a -RMB208M net loss (down 216% year-on-year), explicitly blaming falling substrate selling prices (Stockstar · F902). For 2026 SICC has shifted strategic focus to expanding 8-inch capacity and improving yields at its Shanghai Lingang facility to restore profitability (TrendForce · F1178). Industry reporting describes 8-inch conductive substrate prices falling by roughly two-thirds over the cycle — from around US$1,500 to near US$500 — while the active 2026 price war has moved down to the 6-inch tier, where quotes now sit below US$500 and toward US$400 (TrendForce · F1148); exact figures vary by grade and quarter and should be read as directional. TanKeBlue, despite strong operations, failed three STAR Market IPO attempts (2020, 2023, 2024) and pivoted to a backdoor listing via SOE Tianfu Energy in late 2025 (TanKeBlue · F995). The economics are pure share-over-profit: China is converting an oversupply it helped create into a consolidation lever against higher-cost Western and Japanese incumbents, and accepting losses on the way.
Figure 2 — The same ~two-thirds price collapse that took #1 SICC
into a net loss also drove ex-leader Wolfspeed into Chapter 11; by 2026
the front has moved down to 6-inch substrates priced below US$500.
Source: Stockstar ·
F902, Financier
Worldwide · F889, TrendForce
· F1148.
One step downstream of substrates are the SiC power devices — MOSFETs and modules — that go into inverters. Here China’s offense has a distinctive shape. The largest demand comes from vertically integrated automakers building chips in-house, which removes share from merchant power IDMs entirely.
BYD is the exemplar. On 17 March 2025 it launched its Super e-Platform — described as the world’s first mass-produced full-domain 1000V high-voltage passenger-vehicle architecture — powered by an in-house, mass-produced 1500V automotive-grade SiC power chip, the industry’s first 1500V auto SiC at scale, enabling 1MW flash charging at roughly 2km of range per second (AsiaTechWire · F939). Captivity is the strategic core: BYD Semiconductor supplies 70-90% of BYD’s in-house IGBT and SiC needs — the highest captive ratio of any global auto OEM — and already holds about 28.9% of China’s domestic SiC device market (AsiaTechWire · F939). As BYD gains EV share, that is share lost from Infineon, ST, and onsemi to the system company itself. Geely (Geener Micro), Changan (a JV with StarPower), and Great Wall (Wuxi Xindong) are following the same in-house path (AsiaTechWire · F939).
Merchant Chinese IDMs are scaling alongside them, but the same margin squeeze runs through their financials. CR Micro (688396.SS) grew combined SiC/GaN revenue 3.6x in 2025 and runs both 8-inch SiC and 8-inch GaN platforms in-house, with an auto portfolio spanning 650-1700V SiC MOSFETs already in mass production at domestic OEMs (Hangjianet · F1020). StarPower (603290.SS), China’s only global-leader IGBT-module maker and Changan’s SiC partner, booked record FY2025 revenue of RMB4.012B (+18.3%) yet saw net profit fall about 20% as gross margin compressed from ~31% (2023) to ~26% (2025) through an IDM-transformation and down-cycle trough — and Q1-2026 net profit was cut a further ~74% to a historic low; in H1-2025 it won designations from several leading foreign Tier-1s, launched 8th-gen 1400V IGBT and 2nd-gen 1400V SiC-MOSFET platforms, and began mass delivery of 750V/1200V SiC-MOSFET discretes (StarPower FY2025 · F1159). SiLan (600460.SS) topped out its RMB7B Xiamen 8-inch SiC line on 28 Feb 2025 — about eight months after breaking ground — targeting 420,000 8-inch SiC chips per year by end-2028, and ships SiC and IGBT EV modules in volume to BYD, Geely, Leapmotor, GAC, Dongfeng, and Changan (SiLan · F1021). Sanan (600703.SS), via its 51/49 Chongqing JV with STMicro, is bringing 8-inch auto-grade SiC into risk production, though its FY2025 SiC revenue — RMB910M at Hunan Sanan and RMB29M at the ST JV — confirms the auto-grade line is still early (Futubull · F974); the JV (~480,000 8-inch wafers/yr at full ramp) entered risk production for auto-grade chips in the 2026 8-inch capacity wave (TrendForce · F1187).
The demand pull is real and measured. In 1Q26, global SiC-MOSFET traction-inverter installations reached about 1.17M units (+7.4% year-on-year), and inverters above 550V — the 800V-platform proxy — reached about 920k units (+21%), even as China EV sales fell 19% in the quarter; Western Europe, up 28%, offset the drop (TrendForce · F949). China leads global 800V deployment, with over 15 EV models on 800V as of 2024 and the fastest-growing players all Chinese OEMs — BYD, XPeng, NIO, Geely, Xiaomi, Li Auto (TrendForce · F949).
EV traction is only the first leg. The second is solar and storage, where China already owns the downstream system. Sungrow and Huawei together held over 55% of the global PV-inverter market in H1-2025 (Sungrow #1 at 34.7%), with five of the global top 10 Chinese (pv-magazine · F975). Because Chinese firms control both the SiC device supply and the inverter systems that consume it, PV is a near-fully-localized SiC value chain (pv-magazine · F975).
Gallium nitride is the other wide-bandgap family — GaN-on-silicon on mature 8-inch lines — and here China does not lead a sub-segment, it leads the world. Per TrendForce, China-headquartered Innoscience (2577.HK) held 29.9% of the 2024 global GaN power device market, ahead of Navitas (16.5%), EPC (12.4%), Infineon (10.3%), and Power Integrations (9.8%) (TrendForce · F927). It is the world’s only GaN IDM and the only firm in that top five with a positive trajectory across data-center, automotive, and robotics GaN. On 2023 discrete-shipment volume its lead was wider still, at 42.4% (Omdia · F1010).
| 2024 GaN power device share | Company | Region |
|---|---|---|
| 29.9% | Innoscience | China |
| 16.5% | Navitas | US |
| 12.4% | EPC | US |
| 10.3% | Infineon | Europe |
| 9.8% | Power Integrations | US |
Source: TrendForce (F927).
Figure — Inverts the default ‘China lags’ assumption: on mature
8-inch GaN-on-Si (no EUV, minimal control exposure) China already leads,
~30% vs Navitas 16.5%. Frame as SHARE not scale — Innoscience’s absolute
revenue (~$170M) is tiny next to Infineon. Source: TrendForce
GaN ranking · F1271; Innoscience ·
F726.
Innoscience has the two strongest validators a Chinese champion could ask for. The first is demand, and by mid-2026 it had hardened from a tentative engagement into a firm design win. At COMPUTEX in May 2025, Nvidia named Innoscience the sole Chinese GaN supplier in its 800V HVDC power alliance for next-generation AI data centers — a 14-partner group otherwise made up of Infineon, onsemi, TI, ROHM, STMicro, Navitas, and others — citing Innoscience’s full 800V-to-1V all-GaN conversion chain (TrendForce · F926). What was “testing phase, no formal orders” in late 2025 became, in July 2025, a confirmed selection to supply 800V DC power for Nvidia’s Rubin Ultra GPU (Kyber rack systems), targeted for 2027 commercialization — Innoscience remains the only supplier able to deliver a fully GaN-based 800V-to-GPU chain (15V to 1200V) (Innoscience FY2025/S&P · F1095). One framing caveat survives the upgrade: the Nvidia 800V-HVDC program is a broad 14-company alliance, not a sole-source win — Navitas (supplying both GaN and SiC) and Infineon are confirmed Rubin Ultra/Kyber partners too, and Innoscience’s distinction within the set is being the only full-stack all-GaN supplier and the only mainland-China firm, not exclusivity (Navitas/Nvidia · F1163). The 800V shift matters because a single 1MW AI rack otherwise needs up to 200kg of copper busbar and loses roughly half its power to heat, and rack power is projected to climb from about 120kW today toward 1MW by around 2030 (TrendForce · F926).
The second validator is economics. Innoscience hit a profitability inflection in 2025: H1 gross margin first turned positive at 6.8% (from -21.6% a year earlier), and the full-year comprehensive gross margin came in at +7.3% — its first-ever positive annual gross margin, swinging up 26.8 points from -19.5% in 2024 — on FY2025 revenue of RMB1,213.3M (+46.4%), with adjusted EBITDA turning positive and the basic loss narrowing to RMB840.5M (from RMB1,045.7M) (Innoscience FY2025/S&P · F1095). Capacity targets 60,000 wafers/month by 2027 (from 13,000 in H1-2025), and it has begun large-scale delivery of 48V-to-12V data-center server-board devices. The margin is still thin, and Morgan Stanley sees the company loss-making through at least 2026, but the direction validates the GaN-on-Si IDM model just as the AI pull arrives (Innoscience FY2025/S&P · F1095).
Innoscience also wields IP as offense. In an unresolved global patent war with Infineon, China’s Supreme People’s Court on 12 June 2026 upheld a final injunction barring Infineon from selling its GaN products in mainland China (TrendForce · F996). A Chinese GaN champion can legally exclude the Western leader from the PRC market while Nvidia simultaneously names it the sole Chinese 800V supplier — IP leverage compounding the localization push. The dispute cuts both ways outside China, however: Infineon has won injunctions in Munich and a US ITC infringement finding.
The largest consumer-volume GaN application, fast chargers, is also a fully localized Chinese value chain. That market was roughly US$1.06-1.3B in 2024, about 320M units, and most GaN chargers are assembled in Shenzhen, Dongguan, and Guangzhou for brands led by Anker, Xiaomi, and Baseus (BCC Research · F948). China owns both the device supply (Innoscience) and the downstream assembly.
Image sensors are China’s clearest pure-design win. They are sanctions-resilient by construction — mature nodes, dual-sourceable foundries — and Chinese designers used that insulation to climb the global ranking through the trade war.
The 2024 global CIS ranking by total revenue put Sony #1 (~50%), Samsung #2, OmniVision (Will Semiconductor, 603501) #3 at about 11%, GalaxyCore #4 (~4%), and SmartSens #5 (~3%), with the three Chinese players holding roughly 18% combined (CMBI · F896). Yole’s 2025 refresh confirms the trajectory held into 2025: Sony strengthened toward its 50% target (~46-47% in 2024), Samsung held steady, and the Chinese trio surged — SmartSens led the pack at +105.7% YoY revenue while US/EU players (onsemi, Teledyne, STMicro) lost revenue on industrial/medical/consumer weakness (Yole · F1172). By smartphone shipment volume the Chinese position is even stronger: Counterpoint now ranks GalaxyCore #2 and OmniVision #3 behind Sony, since high-volume low-cost favors GalaxyCore (Yole · F1172). The standout milestone is corporate: OmniVision entered the global top-10 IC design houses in 2025, ranked 8th at about US$3.31B revenue — the sole mainland-China firm on the list — propelled by automotive CIS and new action/360-degree-camera demand (OmniVision Q1-2026 · F1139). The Chinese designers grew fast through 2024-2025: SmartSens posted FY2025 revenue of RMB9.031B (+51.3%) and its first net profit above RMB1B (RMB1.001B, +154.9%), with automotive electronics its fastest line (+113%) as its parts entered European and North American automaker supply chains (SmartSens FY2025 · F1117). The cyclicality cuts both ways, however: GalaxyCore’s FY2025 net profit collapsed to just RMB50.5M (-73%, non-GAAP negative) as a new high-pixel entrant holding price into intensifying mid/low-pixel competition, even as its Lingang 12-inch fab reached mass production of single-chip 50MP CIS (GalaxyCore FY2025 · F1131), and OmniVision pre-announced a softer Q1-2026 (revenue roughly flat-to–4.5% YoY at RMB6.18-6.47B) on weaker consumer/automotive demand and AI-driven memory-supply disruption (OmniVision Q1-2026 · F1139).
| Segment | China position | Detail |
|---|---|---|
| Total CIS (2024 rev) | #3 (OmniVision ~11%), 3 firms ~18% combined | OmniVision passed all but Sony and Samsung (CMBI · F896) |
| Automotive CIS | #1 (OmniVision ~35%) | Surpassed onsemi (33%) after a 37% 2021-24 CAGR (CMBI · F885) |
| Security/surveillance CIS | ~70% (SmartSens + OmniVision) | Pulled by Hikvision and Dahua, the world’s two largest surveillance OEMs (Sigmaintell · F888) |
The automotive win is the standout. The auto CIS market exceeded US$2B in 2024, and OmniVision led with about 35% share (roughly US$820M), having surpassed onsemi after a 37% 2021-24 sales CAGR; onsemi fell to 33% (down 5pp YoY) as its Intelligent Sensing Group declined ~14% in 2024 and a further ~17% in 1H25 amid capacity bottlenecks and China supply-chain localization (CMBI · F885, onsemi 2026 · F1193). onsemi’s response is the same localization play seen across this report — a March 2026 Greater China HQ in Shanghai targeting ~50% localized BOM and an MOU with Innoscience to scale GaN on its 200mm GaN-on-Si line — while SK Hynix is retreating to legacy CIS only to refocus on memory (onsemi 2026 · F1193). The driver is per-vehicle content — an L3 vehicle uses roughly 8-10 cameras — so revenue grows even as the global car build stays flat (CMBI · F942).
Surveillance is where Chinese designers first built scale. SmartSens and OmniVision together held close to 70% of global security-CIS shipments in 2023, pulled by Chinese OEMs Hikvision and Dahua (Sigmaintell · F888). From that base they expanded into mobile and automotive.
The structural reason this held through the trade war is the foundry path. OmniVision runs a fab-lite model, outsourcing wafers to both TSMC and SMIC; the SMIC relationship gives it a domestic, sanctions-insulated second source for the BSI (back-side-illuminated) sensor flow (DigiTimes · F869). Domestic capacity is deepening behind it. Nexchip (688249) is ramping a 12-inch fab toward 100,000 wafers/month at 55nm and 40nm, dedicated mainly to high-end CIS, with SmartSens and Xiaomi as customers (TheNextWeb · F880). GalaxyCore (688728) built China’s first 12-inch CIS specialty fab in Shanghai Lingang (RMB15.5B, 60,000 wafers/month target) and started production at 95% first-batch yield (DigiTimes · F884). Hua Hong’s Wuxi Fab 7 produces CIS alongside eNVM (HKEX · F882). OmniVision is now attacking the flagship-smartphone main-camera tier with parts like the 1-inch OV50X, replacing Sony in Chinese Android flagships (OMNIVISION · F907).
Advanced packaging is where China’s offense and its biggest workaround meet. Globally, TSMC, Intel, and Samsung still hold over 80% of the high-end 2.5D/3D market (SJSemi IPO · F459). But in outsourced assembly (OSAT) Chinese firms are world-scale, and in specific advanced platforms they are at or near the frontier — which lets China partly offset its leading-edge logic gap by integrating mature dies more cleverly.
JCET (Changdian) is the world’s #3 OSAT, at about 10% of the ~US$78.3B 2024 market, behind ASE at 32% and Amkor at 18% (F497). Advanced packaging made up over 72% of JCET’s RMB35.96B 2024 revenue (PR Newswire · F57), and its XDFOI fan-out chiplet platform reached stable mass production in 2024, with the XDFOI 2.5D pilot line supplying international clients with multi-chip products at the 4nm node (PR Newswire · F58). A Chinese OSAT packaging 4nm dies for global customers is a frontier capability, even though China cannot fabricate those dies itself. The AI pull is now visible in the numbers: JCET grew advanced-packaging revenue +35% in 2025 (to ~RMB27B, ~70% of total) and posted a record Q1-2026 of RMB9.17B revenue with net profit up 42.7% YoY on recovering margin, led by computing electronics (+14.2%) and automotive (+28.8%) (JCET Q1-2026 · F1108). Peer TongFu (002156), which assembles >80% of AMD’s GPU/CPU output and is the only mainland firm able to mass-produce HBM3 packaging, grew Q1-2026 net profit +224% YoY — the strongest of China’s big-three OSATs — on FY2025 records of RMB27.92B revenue and RMB1.219B net profit (TongFu Q1-2026 · F1109).
For silicon-interposer 2.5D — the CoWoS-class technology AI accelerators need — SJSemi (Shenghe Jingwei, 688820, formerly SMIC-JCET) held roughly 85% of the mainland China 2.5D packaging market by revenue in 2024 (~8% globally) and is the only mainland company at volume scale in silicon-based 2.5D chiplet processing (SJSemi IPO · F419). Its interposer platform reaches 0.8um/0.8um line/space at up to ~3x reticle size, and its 3D packaging entered mass production in May 2025 (SJSemi IPO · F420). Consistent with the share-over-margin pattern seen in SiC, SJSemi cut its 2.5D wafer price from RMB59,912 (2023) to RMB49,512 (H1-2025) to gain share, with gross margin dipping before recovering as unit cost fell (SJSemi IPO · F421). The capital markets have since validated it emphatically: SJSemi listed on the STAR Market on 21 April 2026 in the largest STAR IPO of the year, raising RMB5.028B; the stock jumped over 400% on day one and climbed past RMB400B market cap by late May, surpassing JCET and TongFu to become the largest A-share OSAT by value, against FY2025 revenue of RMB6.521B and net profit of RMB923M (SJSemi STAR IPO · F1092). SJSemi is also the domestic back-end for China’s HBM chain, packaging and stacking HBM wafers made by XMC (Wuhan Xinxin) — both Entity-listed — though that capacity is still at R&D rather than high-volume scale (SJSemi/XMC · F1185).
This capability is exactly the lever Huawei pulled when barred from TSMC’s CoWoS. The Ascend 910C uses a domestic 2.5D workaround — two compute dies on separate silicon interposers linked by an organic substrate — which is cheaper, higher-yield, and faster to ramp, though it may deliver 10-20x lower die-to-die bandwidth than CoWoS (SemiAnalysis · F172). By 2026 JCET, TongFu, and Huatian all rank among the world’s top-10 OSATs and can integrate Ascend dual-die packaging without foreign help; the binding constraint has shifted to HBM supply and packaging yield (~70%), not interposer line capacity — at ~70% packaging yield SemiAnalysis math implies roughly 600,000 Ascend 910Cs from 2026’s ~7M HBM stacks, matching Huawei’s stated ~2x-2025 target (SemiAnalysis · F1126). Packaging does not erase the logic gap, but it lets China build a competitive accelerator out of dies it can actually obtain.
One caveat keeps this from being a clean sweep: the assembly capability China has localized still rests on packaging materials it has not. Even as Chinese OSATs scale 2.5D/3D, the capillary underfill that flows under flip-chip AI dies remains a tight Henkel/Namics/Resonac oligopoly with minimal qualified Chinese supply at advanced nodes (ReAnIn · F969), and the high-end advanced-packaging epoxy molding compound, plus the copper foil and glass cloth beneath the substrate, are Japan-led (F968, F1015). The capability is localized; some of the consumables underneath are not.
Pull the four families together and one economic signature repeats. China builds aggressive capacity, prices to take share, and accepts thin or negative margins on the way, betting that the demand curve — EV 800V, solar, AI 800V-HVDC, ADAS cameras — is steep enough to reward whoever holds the volume. TrendForce flagged exactly this divergence for 2026: GaN-RF demand surging while SiC profitability stays under pressure from the substrate price war and ~50% upstream utilization, visible in SICC’s FY2025 loss, StarPower’s ~74% Q1-2026 profit drop, GalaxyCore’s collapse to near-zero net profit, and Innoscience’s still-thin full-year +7.3% gross margin (TrendForce · F1022, Innoscience FY2025 · F1095). TrendForce’s broader 2026 read is that the SiC land-grab phase is maturing from raw capacity expansion into a yield/cost/large-diameter execution race, where 8-inch capability and AI/HPC thermal-material demand become the differentiators (TrendForce · F1187). China holds the largest single GaN-power share and the #1 conductive-SiC-substrate position heading into the steepest part of the demand curve, but the price aggression that captured the share has compressed the profit (TrendForce · F1022). The prize is large: the GaN power market is modeled to grow from US$271M (2023) toward roughly US$4.4B by 2030, and SiC devices toward about US$10B by 2030 (TrendForce/Yole · F1022). Whether the land grab pays off depends on whether China’s champions can outlast the down-cycle they created.
Export controls have a blind spot, and China is exploiting it deliberately. SiC, GaN, CIS, and advanced packaging all run on mature lines outside the EUV/leading-edge control perimeter (Omdia · F1010, Yole · F872). In these families China is not catching up; it already leads or co-leads global share. The controls shape where the contest happens, not who wins it everywhere.
China already holds global #1 positions: Innoscience in GaN power (29.9%), SICC in conductive SiC substrates (27.6%), OmniVision in automotive CIS (~35%) (TrendForce · F927, Stockstar · F902, CMBI · F885). These are not aspirational targets; they are current rankings against the firms that pioneered the markets.
The binding constraint is profitability, not capability. SICC posted a net loss, StarPower’s Q1-2026 profit fell ~74%, ST’s profit collapsed, and Wolfspeed went bankrupt and is still loss-making (-27% to -46% GAAP gross margin) two quarters after emerging from Chapter 11; even Innoscience’s first positive full-year gross margin is only +7.3% (Stockstar · F902, StarPower · F1159, Wolfspeed · F1110, Innoscience · F1095). The risk to the thesis is financial endurance, not technical lag.
Captive vertical integration is quietly destroying the merchant power-IDM market. BYD makes 70-90% of its own SiC/IGBT, and other Chinese OEMs are copying it (AsiaTechWire · F939). As Chinese EVs gain share, Infineon, ST, and onsemi lose a market that simply ceases to be merchant.
Western incumbents are localizing into China, not exiting, which entrenches the shift. onsemi sources GaN from Innoscience and targets ~50% China BOM; ST builds SiC with Sanan (TrendForce · F1009). The battleground is moving onshore, on China’s cost terms.
Packaging is a genuine lever but rests on materials China has not yet localized. JCET (4nm XDFOI, +35% advanced-packaging revenue in 2025) and SJSemi (~85% mainland 2.5D, now China’s largest A-share OSAT after its >RMB400B-cap April-2026 STAR IPO) let Huawei route around the CoWoS ban (JCET · F1108, SJSemi STAR IPO · F1092), but underfill, advanced EMC, and substrate inputs remain Japan/Western-gated (ReAnIn · F969) — and the binding constraint on Ascend output is now HBM supply and ~70% packaging yield, not interposer capacity (SemiAnalysis · F1126). A residual dependency even in a winning column.
Earlier deep dives traced how China narrowed the hardware gap: SMIC’s 7nm process, Huawei’s Ascend line, a wave of GPU start-ups now reaching A100-class silicon. The harder problem sits one layer up. The constraint most likely to outlast export controls is not the chip but the software that makes a chip usable — the compiler, the kernel libraries, the framework integration, and above all the network of outside developers whose accumulated work turns raw silicon into a platform. Nvidia’s CUDA is that platform, built over roughly two decades (InfoQ/The Register · F937). China’s reply is not one rival platform but six or more incompatible ones, and that split is the core weakness. Two claims follow. First, the CUDA moat is layer-dependent: shallow where most developers work (the PyTorch framework layer) and deep where the performance lives (the optimized kernel layer). Second, the binding long-run constraint is fragmentation — a single CUDA pools the work of millions of developers, while China’s effort is divided across stacks that cannot share that compounding. The paradox is that the same export controls and state mandates throttling China’s hardware are also the fastest force unifying its software.
The popular framing of CUDA’s moat — “a million developers, twenty years, twenty-three thousand supported models versus a few hundred” — is real but hides where the difficulty actually lies. A more precise model, drawn from a Chinese-language translation of a Register analysis, is that the moat varies by layer (InfoQ/The Register · F937).
At the high-level framework layer, the moat is shallow. Most machine-learning engineers write PyTorch, TensorFlow, or JAX, not raw CUDA kernels; an Intel executive quoted in the same analysis argues that a working PyTorch backend therefore captures most users (InfoQ/The Register · F937). That is why every serious Chinese vendor races to ship a PyTorch device extension — the framework layer is the cheapest place to intercept developers.
At the low-level kernel layer, the moat is deep and stubborn. Optimized kernels must be ported, refactored, and re-tuned; some Nvidia hardware-specific calls have no equivalent on other silicon; and automatic porting is imperfect — AMD’s HIPIFY mishandles texture-memory and multi-header cases, and Intel’s SYCL claims roughly 95% coverage, leaving a long tail (InfoQ/The Register · F937). On top of this sits what the analysis calls a “software compatibility minefield”: aligning matching versions of Python, PyTorch, BitsAndBytes, Flash-Attention, Triton, and vLLM is hard on Nvidia and worse on non-Nvidia stacks that must recompile each component (InfoQ/The Register · F937).
The strategy falls out of this geometry. Because the framework layer is shallow, China bets on framework-level capture — PyTorch extensions such as torch_npu for Ascend and torch_musa for Moore Threads, plus a Triton-based operator library (FlagGems). Because the kernel layer is deep, China invests in automatic transcompilers to grind down the per-operator porting cost (Sections 4 and 6). The real chokepoint is the long-tail operator problem: the thousands of custom kernels each new model introduces, not the headline GEMM and attention kernels. Most of the domestic engineering effort is aimed there.
China does not have one CUDA alternative; it has at least six, each with a different relationship to the moat it is trying to cross. The table maps how each ports CUDA workloads and where its dependency sits.
| Vendor / stack | Architecture type | CUDA-porting mechanism | Library mapping | Inherited dependency |
|---|---|---|---|---|
| Huawei CANN + MindSpore | NPU (Ascend) | Rewrite kernels in Ascend C; PyTorch via torch_npu (PrivateUse1) (PyTorch · F765) | HCCL=NCCL, aclNN=cuDNN/cuBLAS, Ascend C=CUTLASS, Graph Engine=TensorRT (Ascend academic · F727) | Self-built; no binary CUDA compatibility (Ascend academic · F727) |
| Moore Threads MUSA / torch_musa | GPGPU (CUDA-clone) | Device string cuda→musa; mify
auto-converts .cu; mcc is
nvcc-syntax-compatible (Moore Threads ·
F960) |
muBLAS=cuBLAS, muFFT=cuFFT, muDNN=cuDNN (Moore Threads · F747) | CUDA-inheritance (PTX-level translation) (Moore Threads · F747) |
| MetaX MACA (MXMACA) | GPGPU (CUDA-clone) | Dual path: Triton adaptation + CUDA-to-MACA migration; vLLM-metax
cuda_alike backend (MetaX · F757) |
Mirrors CUDA drivers/compilers/operator libraries (MetaX · F757) | CUDA-inheritance (MetaX · F757) |
| Cambricon NeuWare | NPU/ASIC | Rewrite in BANG C; CNCC compiler→MLISA via CNAS (Cambricon · F961) | CNRT=CUDA Runtime, CNDrv=CUDA Driver, CNPerf/CNStudio=nvprof/Nsight (Cambricon · F961) | Self-built; no source/binary CUDA compatibility (Cambricon · F961) |
| Hygon DTK (DCU Toolkit) | GPGPU | hipify (CUDA→HIP), exactly as on AMD (Hygon
· F921) |
MIOpen=cuDNN, RCCL=NCCL (Hygon · F921) | AMD ROCm, not CUDA (Hygon · F921) |
| Iluvatar IXUCA | GPGPU | Recompile native CUDA with Iluvatar Clang; no rewrite for most code (Iluvatar · F840) | +corex-tagged torch/triton/vllm builds; IxRT=TensorRT
(Iluvatar ·
F840) |
CUDA-inheritance (recompile) (Iluvatar · F840) |
Three observations follow. First, the vendors split into CUDA-inheritance plays (MUSA, MACA, IXUCA), which minimize porting friction to absorb existing CUDA developers, and self-built clean-room plays (CANN, NeuWare), which run full toolchains with no CUDA compatibility and demand kernel rewrites. Second, Hygon is the odd one out: by forking AMD’s ROCm and using the HIP programming model, its software risk is tied to ROCm’s maturity, not CUDA’s — a genuinely different dependency profile. That fork also carries a hardware detail that breaks naive porting, since the DCU groups 64 threads per wavefront like AMD, versus Nvidia’s 32-thread warp (Hygon · F921). Third, and most important: none of the six is compatible with any other. A kernel hand-tuned for MUSA does nothing for CANN; an Ascend C operator is useless on a Cambricon MLU.
A maturity snapshot makes the framework-capture strategy concrete. Moore Threads’ open-source torch_musa exposed 1,050+ MUSA-exclusive operators by v2.7.0 (28 November 2025) and was the first domestic GPU to support native FP8 (v2.0.0, May 2025) (Moore Threads · F960); the project has since reached v2.9.0 (March 2026) (Moore Threads/GitHub · F960). The framework-capture payoff is now visible at the model layer: the flagship MTT S5000 runs DeepSeek V4 natively (~4,000 tokens/s prefill, ~1,000 tokens/s decode) and reached full-stack compatibility with Alibaba’s Qwen3.5 series — and Moore Threads is targeting ~500,000 accelerator shipments in 2026, up from ~116,000 in 2025 (SCMP · F1181). Huawei’s CANN, by contrast, supported only around 160 mainstream models in a mid-2025 Chinese analysis, against CUDA’s 23,000-plus models and 1M-plus developers. The figure is a single analyst’s framing rather than a verified census, but it captures the order of magnitude on the gap (Sina Finance · F512).
The clearest diagnosis of why fragmentation is structural rather than incidental comes from inside China. Tsinghua academician Zheng Weimin (郑纬民) describes the non-CUDA AI-chip field as 小散弱 — “small, scattered, weak” — and traces it to four causes: non-unified instruction sets and fragmented hardware architectures; non-unified software stacks with high user learning cost; low operator coverage and high migration cost; and vendors each fighting their own battle with too little ecosystem competitiveness (icsmart.cn · F946).
Zheng attaches a number that anchors the whole report: for large-model training, domestic AI chips reach only about 60% of foreign-chip performance, but if ten software areas were each done well — programming frameworks, parallel acceleration, communication libraries, operator libraries, AI compilers, programming languages, schedulers, memory allocators, fault-tolerance systems, and storage systems — customers would be satisfied (icsmart.cn · F946). The framing is the argument: the gap is ten software problems, not one silicon problem.
He also names the deeper asymmetry. CUDA grew through a global third-party developer flywheel — a hardware → driver → software → application cycle in which outside contributors fixed bugs and filled gaps. Domestic GPUs remain vendor-led with low third-party participation, so driver updates depend on each vendor’s own testing and react slowly to niche needs (icsmart.cn · F946). This is the economic core of the moat: a single CUDA captures the network effects of every developer who ever optimized against it, while six domestic stacks split that pool six ways and none reaches critical mass. The problem is officially recognized — a Domestic AI Chip Software Ecosystem White Paper (国产AI芯片软件生态白皮书), led by Hunan University with Zhipu AI, Tsinghua, BUPT, H3C, and SUSTech, was published in November 2025 to benchmark and coordinate the fragmented stacks (CANN, NeuWare, DTK, MUSA, MACA, IXUCA) (QiMeng-Xpiler/white paper · F843).
Figure 1 — Six incompatible stacks force every model to be re-ported
to every vendor (N×M); one portable layer collapses that to N+M and lets
developer effort compound — the network-effect logic behind both CUDA
and the FlagOS bid. Source: BAAI/FlagTree · F890;
icsmart.cn · F946.
If the diagnosis is fragmentation, the prescription is a neutral, multi-vendor layer that pools network effects across incompatible chips. China is pursuing this on two fronts: a transcompiler-and-operator front led by the state-backed Beijing Academy of Artificial Intelligence (BAAI), and a framework front led by Baidu.
BAAI FlagOS is the flagship. FlagOS 2.0, unveiled at the 2026 Zhongguancun Forum, supports 20+ processor types and was co-developed by BAAI with Peking University, Tsinghua, the Chinese Academy of Sciences, and 10+ chip makers (BAAI/FlagTree · F890). Its design goal is explicit: convert the N-vendors × M-models porting matrix into an N+M open ecosystem — write once, run on any supported chip (BAAI/FlagTree · F890). The core components are:
triton-lang/triton that targets many backends from one
source. Its published backend list already spans Nvidia, AMD, Hygon,
Moore Threads, Huawei Ascend, Cambricon, Iluvatar, MetaX, Kunlunxin, and
Enflame, among others (BAAI/FlagTree ·
F890).The key move is that FlagGems makes Triton the de-facto portable kernel IR. Because the kernels are written in hardware-neutral Triton and routed through ATen, a single FlagGems install can serve any backend whose Triton compiler targets that chip — turning a US-originated abstraction into the layer under which China unifies (PyTorch.org · F990). This is the most credible bid to borrow CUDA’s network effects rather than rebuild them: instead of asking developers to learn BANG C, Ascend C, or MUSA, it inserts a Triton operator layer beneath unmodified PyTorch. The visible risk is that Triton is itself an OpenAI/Nvidia-originated project, so the strategy depends on an upstream the US could in principle steer — though Triton is permissively licensed, and the FlagTree fork is the hedge against that dependency (PyTorch.org · F990).
Baidu PaddlePaddle attacks the same problem from the
framework side. PaddleCustomDevice is a plug-in hardware-abstraction
layer that decouples accelerator backends from the core framework. In
Paddle 2.6 the team removed Ascend NPU and Cambricon MLU vendor code
from the core and migrated it out-of-tree, so a model now runs
identically across chips by changing only the device string —
npu, mlu, xpu, dcu,
gcu — with no other code change (PaddleCustomDevice
· F909). Supported backends span Huawei Ascend, Cambricon,
Kunlunxin, Hygon, Enflame, Biren, Intel, Apple, and Tecorigin (PaddleCustomDevice
· F909). Paddle 3.0 (May 2025) adds CINN, a built-in neural-network
compiler that does automatic operator fusion and code generation — the
domestic counterpart to PyTorch’s torch.compile/Inductor —
with reported gains of roughly 30% on Llama2 and Stable Diffusion via op
fusion, though the vendor cautions that real models gain less (PaddlePaddle
· F910). A compiler that generates fused kernels per backend is
exactly what lowers the long-tail-operator porting cost, letting
domestic chips avoid writing a full cuDNN by hand (PaddlePaddle
· F910).
The two efforts are complementary. FlagOS makes the compiler and operator layer portable; Paddle makes the framework the portability layer. Both shrink the matrix of N vendors times M models to something an ecosystem can sustain.
By early 2026 Huawei was pursuing the same borrow-don’t-rebuild logic from inside its own clean-room stack. CANN 8.0, current at MWC March 2026, now natively supports PyTorch, vLLM, SGLang, xLLM, verl, Triton, and TileLang — meaning the serving stack (vLLM/SGLang), the RL stack (verl), and both hardware-neutral kernel DSLs (Triton, TileLang) all reach Ascend through CANN, so developers arrive via the frameworks they already use rather than learning Ascend C (Huawei MWC · F1158). Combined with the March-2026 open-sourcing of CANN itself (Section 8), this is the most concrete version of the network-effect bid running on a single-vendor stack — though Huawei still concedes CANN’s developer experience trails CUDA’s 15-plus years of ecosystem (Huawei MWC · F1158). Notably, the same Triton-and-TileLang layer that FlagOS and DeepSeek use to span chips is now a first-class CANN target, so the neutral kernel-IR and the vendor stack are converging on the same abstraction.
The strongest operational counter-example to the fragmentation thesis is a launch-day event. The FlagOS community reports completing full adaptation and inference deployment of DeepSeek-V4-Flash across 8+ domestic AI chips on the same day — Hygon, MetaX, Huawei Ascend, Moore Threads (FP8 on the MTT S5000), Kunlunxin, T-Head Zhenwu, Iluvatar, and Nvidia (BigGo Finance · F899). The mechanism is the one Section 4 describes: FlagGems, described as the world’s largest single Triton operator library, replaced all operators in the inference pipeline and “completely eliminated dependence on CUDA operators,” so one model lit up many incompatible chips at once rather than requiring N separate vendor ports (BigGo Finance · F899). FlagOS-Tune auto-tuning of the S5000 FP8 path reportedly cut time-to-first-token latency 16.5%, cut inter-token latency 39.7%, and raised throughput 65.7% (BigGo Finance · F899). These vendor-reported figures should be read as directional rather than independently audited — the finding carries medium confidence — but the day-zero multi-chip adaptation is the proof of concept that matters.
The serving frameworks are becoming a second portability layer.
vLLM’s Hardware-Pluggable RFC lets accelerators integrate as out-of-tree
plugins, and vLLM now lists Huawei Ascend, MetaX, Rebellions, and others
among supported plugins, with vllm-ascend the canonical example (vLLM RFC ·
F984). SGLang added initial Ascend NPU support in 2025 and in early
2026 proposed its own hardware-plugin system, explicitly because
scattered if _is_npu: guards had become unsustainable as
more vendors sought integration (vLLM RFC ·
F984). The catch, which exposes the dependency problem in miniature,
is that on Ascend SGLang still required vLLM as a prerequisite, and a
torch==2.6.0 limit pinned it to a specific vLLM version (vLLM RFC ·
F984). China gets serving-framework reach largely for free by
upstreaming plugins into US-led open-source projects — a faster on-ramp
than building a serving stack per vendor.
Framework capture handles the shallow layer; the deep kernel layer needs different tools. Two research directions aim to drive the per-operator porting cost toward zero.
The first is automatic transcompilation — machine-translating CUDA kernels into domestic instruction sets. QiMeng-Xpiler pursues cross-system tensor-program transcompilation through a neural-symbolic approach (QiMeng-Xpiler · F843), and AscendCraft does Ascend-specific kernel generation through DSL-guided transcompilation, using a domain-specific-language intermediate to constrain the search and reduce hallucinated operators (AscendCraft · F987). The logic is that the binding chokepoint is the thousands of long-tail custom kernels each model introduces — which manual tools like MUSIFY, hipify, and hand-written Ascend C cannot cover at scale — so the scalable answer is to treat kernel porting as a translation problem (AscendCraft · F987).
The second is a portable kernel DSL (domain-specific language). TileLang, backed by DeepSeek, is a composable tiled programming model that separates dataflow from scheduling through annotations, letting one kernel be written hardware-agnostically and retargeted by the compiler (TileLang arXiv · F1013). Its measured results are strong: roughly 1.03–1.25× over Triton on GEMM, 1.41× on FlashAttention, and an MLA kernel in about 70–80 lines of Python reaching some 98% of hand-optimized FlashMLA — CUTLASS-class performance at Triton-level usability (TileLang arXiv · F1013). For the domestic moat, the key move is that TileLang added AscendC and Ascend-NPU-IR backends on 29 September 2025 alongside AMD-HIP and Apple-Metal targets, and DeepSeek open-sourced TileLang-based operators in V3.2-Exp (TileLang arXiv · F1013). Unlike DeepSeek’s earlier V3 work, which used hand-written PTX and locked it tighter to Nvidia, TileLang lets the same kernel source target Nvidia, AMD, and Ascend — attacking the per-architecture rewrite tax at the language level.
The other side of the software lever is co-design: reshaping the model to fit constrained domestic silicon rather than waiting for the silicon to match Nvidia. DeepSeek V4 (released 24 April 2026) was the first DeepSeek model built around Huawei Ascend from the outset. It shipped in two flavors — V4-Flash (284B-parameter MoE, 13B active) and V4-Pro (1.6T-parameter, 49B active, trained on 33T tokens) — and Huawei adapted the entire Ascend SuperNode line (A2, A3, and 950 series) for V4 inference day-zero on the strength of pre-launch co-design (The Register · F1127). Huawei and DeepSeek co-developed CANN fused operators and exploited the Ascend dual-core design so the official API served V4 on Ascend SuperNodes from day zero, with the model using FP4 precision matched to the Ascend 950PR, the only domestic chip supporting that compact format (KB · F740). The pricing makes the co-design payoff concrete: V4-Pro at USD3.48 and V4-Flash at USD0.28 per million output tokens (against roughly USD30 for OpenAI and USD25 for Anthropic), with DeepSeek signalling further cuts once Ascend 950 SuperNodes ship at scale in H2-2026 (The Register · F1127). Demand for the inference silicon followed the model directly — Huawei moved the Ascend 950PR into mass production in April 2026 and raised its price ~20% on the post-V4 demand surge, with a ~750,000-unit 2026 target and a ByteDance commitment of over USD5.6B in Ascend spend (Reuters/TradingView · F1051).
The training picture stays nuanced, and this is the load-bearing qualifier. The V4 technical report notes only that DeepSeek validated its fine-grained expert-parallel scheme on both Nvidia GPUs and Ascend NPUs; multiple readings (MIT Tech Review) hold that V4 was still trained mainly on Nvidia, with only part of training — and only part of V4-Flash — moved to Huawei chips (The Register · F1127). A Huawei-led team separately claims full-parameter post-training of the 1.6-trillion-parameter V4-Pro on a cluster of 1,000+ Ascend 910C chips (KB · F740). The inference-vs-training split that defined the R2 episode therefore persists into V4: day-zero inference on Ascend, frontier pre-training still leaning on Nvidia.
A critical limit keeps this honest. An earlier DeepSeek R2 attempt could not complete a single successful training run on Ascend even with Huawei engineers on-site; unstable performance, slow interconnect, and CANN gaps forced a fallback to Nvidia for training, leaving Ascend on inference (KB · F740). The pattern is consistent: Ascend is now credible for inference, while frontier pre-training from scratch on domestic silicon remains unproven — and that gap is a software gap (operator coverage, interconnect libraries, stability), not a raw-FLOP gap.
Software can also be played as offense against a hardware restriction. Huawei’s Unified Cache Manager (UCM), revealed 12 August 2025, tiers the LLM KV-cache across HBM, DRAM, and SSD to speed up inference without leaning on scarce HBM — reportedly up to 90% lower latency and up to 22× higher throughput by reorganizing the memory hierarchy in software rather than matching Nvidia’s HBM bandwidth (Epoch AI · F1005). Clever software is becoming a lever to extract more from constrained silicon — the deeper-moat dynamic running in reverse.
The strongest external case that software, not silicon, is the binding constraint comes from Epoch AI and RAND. The hardware gap is closing: in DeepSeek testing the Ascend 910C reached roughly 60% of an H100’s measured throughput, about 593 TFLOP/s — which is itself around 80% of the 910C’s own theoretical ceiling of ~752 TFLOP/s (Epoch AI · F985). At system level, Huawei’s CloudMatrix 384 aggregates many chips to compete with Nvidia rack-scale systems, though its custom interconnect reaches less than half NVLink’s bandwidth, and the system runs at higher cost and power (Epoch AI · F985). Yet adoption resists: in 2024 Chinese firms bought roughly 1M Nvidia GPUs (chiefly H800 and H20) against far fewer domestic Ascend parts, and only a handful of state-backed users trained on Huawei (Epoch AI · F985). Epoch frames two bottlenecks — chip manufacturing, held back by equipment controls, and a weaker software ecosystem that is bug-prone, poorly documented, and unstable — and judges the software one more durable: even if export controls lift, immature accelerator software remains, and each roadblock takes years to clear (Epoch AI · F985). The adoption gap despite good-enough hardware is the key evidence — the silicon exists, the mature stack does not. One counterpoint, from Dylan Patel of SemiAnalysis, is that in a hundred-billion-dollar AI-capex world, all moats are shallower than ever (Epoch AI · F985).
The closing paradox is that export controls are themselves the fastest unifier. When Chinese developers can no longer buy Nvidia hardware, they stop writing CUDA and build on Ascend/CANN/MindSpore — a stack that did not exist at scale three years ago (Bruegel · F802). Policy forced the migration: an August 2025 rule required data centers to source at least 50% of chips locally, and by November 2025 state-funded projects were barred from foreign accelerators entirely, with builds under 30% complete told to rip out already-installed Nvidia hardware (Bruegel · F802). The result is a learning loop — not because CANN matched CUDA, but because four conditions now hold together: a protected market large enough to sustain an immature ecosystem, a state-backed open-source contributor pipeline, falling switching costs through PyTorch compatibility, and flagship open-weight models running on Ascend (Bruegel · F802). Huawei’s own move underlines the diagnosis. Its late-2025 pledge to open-source the CANN toolchain — described in earlier drafts as a future commitment for end-2026 — was actually delivered at MWC Barcelona in March 2026: Huawei open-sourced CANN through layered decoupling (operator libraries, acceleration libraries, graph engines, and programming languages) and published the UnifiedBus 2.0 technical specification alongside it (Huawei MWC · F1101). That is a recognition that closed, single-vendor control cannot bootstrap CUDA-scale network effects — the same logic driving FlagOS as a neutral host (MindSpore · F1006).
A natural question is whether the moat is about to be automated away: if a large language model can write GPU kernels and porting code, the long-tail-operator tax that is the deep moat should collapse. The 2025–2026 evidence says the relief is real but partial — and asymmetric in a way that does not simply hand the advantage to China.
What the tools can do separates into three bars: a kernel that runs, one that is correct, and one that is performance-competitive with an expert’s. The first is nearly solved — frontier models compile 93–99% of generated CUDA (CUDABench · F1211). The second is increasingly automatable through agentic generate-profile-repair loops: an NVIDIA closed-loop workflow reached 100% correctness on KernelBench Level 1 and 96% on Level 2 (NVIDIA · F1225). The third is the hard, unsolved part: even the best 2026 models reach only ~40% of a GPU’s roofline against ~78% for an expert-tuned kernel — roughly a 2× performance tax — and only about a fifth of one-shot kernels beat the compiler baseline (CUDABench · F1221; KernelBench-X · F1222). Headline speedups must be discounted for benchmark gaming: Sakana AI’s “AI CUDA Engineer” claimed 10–100× before admitting its pipeline exploited an evaluation loophole, and a cleaned harness cut average speedups from ~3.1× to ~1.5× (TechCrunch · F1209; robust-kbench · F1234).
For China the help lands on the right layer. The bottleneck is the porting tax across six-plus fragmented stacks, and automation attacks the fixed cost of coverage. The flagship Chinese transcompiler, QiMeng-Xpiler (ICT/CAS, OSDI 2025), machine-translates tensor programs at ~95% accuracy across CUDA, AMD HIP, Intel VNNI and — critically — Cambricon’s BANG, at up to 2× over vendor-tuned libraries (QiMeng-Xpiler · F1241). Triton is the lingua franca that collapses the N×M porting matrix: BAAI’s FlagGems ships 180-plus auto-generated Triton operators that run across NVIDIA, Moore Threads, MetaX, Iluvatar and Kunlunxin (FlagGems · F1216), and LLMs that write correct Triton now match frontier quality at 8B parameters (AutoTriton · F1246). The gap is sized: Huawei’s CANN auto-converts ~65% of PyTorch operators, leaving a ~35% long tail of hand-written Ascend C — exactly the tail codegen can shrink (CANN porting · F1255). And AI is most useful for greenfield bring-up of a new stack with no reference library — China’s situation — and least useful for out-tuning decades of cuDNN (KForge · F1231).
But three forces keep the moat from dissolving, and two cut against China. First, the residual after auto-porting is the genuinely hard custom long tail, where generated performance tops out near 40% of roofline — correct coverage, persistent performance tax (AscendCraft · F1232). Second, generation quality scales with how much training code exists for a backend, so models are far better at CUDA than at any Chinese stack — the tool helps the data-rich incumbent most, exactly where China is weakest (AscendKernelGen · F1215; MultiKernelBench · F1210). Third, the deepest moat assets — the verification harness, fifteen years of reference kernels, the reward data the agentic loops train on — accrete on NVIDIA first, so the same techniques improve the leader at least as fast (SemiWiki · F1218; ChinaTalk · F1238). The field check: when DeepSeek tried to train on Ascend in 2025 it reverted to Nvidia for training after repeated failures, keeping Ascend for inference — automation had not bridged the training-software gap (Tom’s Hardware · F1242).
The net read: generative AI makes the framework and correctness layers of the moat materially less severe for China — already-visible relief in same-day multi-chip model migration, ~95% transcompilation, and near-solved correctness on common operators — and it lowers the fixed cost of running fragmented stacks. It does not yet dissolve the deep moat, which is expert-competitive performance on the hard long tail plus a trustworthy verification harness — both still ~2× gaps, unsolved, and structurally favoring whoever owns the most reference data and tooling, today NVIDIA (ChinaTalk synthesis · F1219). It compresses the moat on the most automatable dimension while leaving the hardest one largely intact — with a demand-side irony: better AI raises compute demand, which China is supply-constrained on (HBM, advanced logic), so software relief that outruns silicon supply only relocates the bottleneck.
Software, not silicon, is the binding long-run constraint. The hardware gap is at roughly 60% and closing; the adoption gap persists because the mature, stable, documented software stack does not yet exist, and that gap is judged more durable than the manufacturing one (icsmart.cn · F946; Epoch AI · F985). For the capability-then-investment argument, capability at the software layer lags the capital and the silicon — this is where the multi-year risk sits.
The CUDA moat is layer-dependent, and China is attacking it where it is shallow. Framework-level capture (torch_npu, torch_musa, FlagGems-on-ATen) intercepts most developers cheaply; the deep kernel layer is being ground down by transcompilers and a portable kernel DSL rather than out-recruited developer by developer (InfoQ/The Register · F937; PyTorch.org · F990; TileLang · F1013).
Fragmentation is the real weakness, and it is structural. Six-plus incompatible stacks cannot pool network effects the way one CUDA does; the official Chinese diagnosis (小散弱, ten software gaps, weak third-party developer participation) and a national white paper both name fragmentation directly (icsmart.cn · F946; white paper · F843). Any investment view should track consolidation, not just per-vendor progress.
The unification push has produced a working proof of concept but unproven scale. FlagOS lit up 8+ chips with one model on launch day by routing through Triton operators, and Paddle makes the framework itself the portability layer — but the load-bearing claims (FlagOS-Tune speedups, day-zero adaptation) are vendor-reported and medium-confidence, and the version-lock minefield persists (BigGo Finance · F899; PaddleCustomDevice · F909).
Inference is solved enough; frontier training is not. DeepSeek V4 (April 2026) served on the full Ascend SuperNode line from day zero, but its own technical report only validates the expert-parallel scheme on Ascend, and the model was still trained mainly on Nvidia (The Register · F1127); the earlier R2 attempt could not complete a single training run on Ascend (KB · F740). Together these are the clearest evidence that the remaining gap is software (operator coverage, interconnect, stability), and that domestic chips are an inference story until that closes.
Export controls and state mandates are paradoxically the cure. By forcing developers off Nvidia and onto domestic stacks, and by guaranteeing a captive market large enough to sustain an immature ecosystem, the controls are the fastest force unifying China’s software — the same policy that throttles the hardware is accelerating the software flywheel (Bruegel · F802). The flywheel is now visible in execution rather than pledge: Huawei delivered its CANN open-sourcing and the UnifiedBus 2.0 spec at MWC March 2026, and CANN 8.0 broadened its on-ramp to vLLM/SGLang/verl/Triton/TileLang — a single-vendor stack reaching for CUDA-style network effects (Huawei MWC · F1101; Huawei MWC · F1158; MindSpore · F1006).
China’s chip drive is usually told as a supply story: who can etch a transistor, who can pattern it without an EUV scanner. This deep dive looks at the other side of the ledger — who pays for the build-out and who buys what comes off the line. The short answer is that demand and capital in China’s accelerator economy are increasingly manufactured by the state rather than discovered in an open market. The AI-server market is doubling, and it is large — China server-market revenue alone hit USD19.2 billion in Q1 2026, up 30.9 percent year-on-year (IDC/InfotechLead · F1194) — but it flows through a handful of hyperscaler buyers, a thin-margin server-OEM channel, and a procurement ladder that mandates domestic silicon. Behind it sits the largest industrial-policy chequebook in the world — Big Fund III at RMB344 billion (CSRC/中证网 · F708) — scarred by a corruption probe that jailed its own leadership (Caixin · F556) and a history of zombie-fab fraud (SemiAnalysis/talent record · F691t). The capital is patient and vast; the demand is captive and concentrated. The binding constraint on both is no longer money but fab capacity, memory, and people. Capability comes first; only then can the investment find a return. That sequencing is the thread running through everything below.
The headline number is large. Per IDC’s China Semi-Annual Accelerated Computing Market tracker, the China accelerated-server (AI-server) market reached about USD16 billion in H1 2025, more than doubling year-on-year (+100 percent) from about USD5 billion in H1 2024, with accelerated-chip shipments topping 1.9 million units in the half. The momentum carried into 2026: IDC’s Q1 2026 data put China’s overall server-vendor revenue at USD19.2 billion, up 30.9 percent year-on-year, and IDC now models China’s accelerated-server market growing at the world’s fastest five-year CAGR of about 41.5 percent and exceeding about USD140 billion by 2029 — within a global AI-infrastructure spend reaching USD758 billion by 2029, of which accelerated servers are 94.3 percent (IDC/InfotechLead · F1194). That is a demand curve steep enough to justify almost any supply-side bet, if it is real and if it is reachable.
Figure 1 — China’s AI-server demand more than doubled in a year and
is forecast to grow roughly 9x by 2029 (about 41.5 percent CAGR).
Source: IDC · F854;
refreshed Q1 2026 actuals and 2029 TAM IDC/InfotechLead
· F1194.
It is real, but it pours through a narrow throat. By IDC’s H1 2025 industry breakdown, the internet sector — the big hyperscalers ByteDance, Alibaba, Tencent and Baidu, plus other cloud providers — was the single largest buyer at nearly 69 percent of the accelerated-server market. Finance, education, telecom and healthcare each grew over 100 percent year-on-year, but off small bases (IDC/Caixin · F858). The same data show the home-grown tilt taking hold: domestic-brand accelerators rose to about 35 percent of the H1 2025 market by brand, and non-GPU accelerators — NPUs, ASICs and FPGAs — captured about 30 percent, growing far faster than GPUs. A year earlier, non-GPU accelerated servers were only about USD0.7 billion against USD4.3 billion of GPU servers, yet already up 182 percent (IDC/Caixin · F858). The tilt accelerated through the rest of the year: by full-year 2025 domestic chip brands had climbed to about 41 percent of the China market (IDC/InfotechLead · F1194). The tilt toward domestic NPUs and ASICs is therefore not a forecast. It is already in the brand mix.
The largest disclosed private demand anchor is Alibaba. At its September 2025 Apsara conference and on later calls, CEO Eddie Wu said the company will overshoot its original three-year RMB380 billion (about USD53-56 billion) AI-infrastructure plan and is preparing a larger one, chasing a roughly USD100 billion annual cloud-plus-AI revenue target. Its March-2026 quarter (FY2026 Q4) confirmed the trajectory: Cloud Intelligence Group revenue reached RMB41.6 billion (about USD6.0 billion, +38 percent year-on-year), with AI-related cloud products at an annualised run-rate near USD5.2 billion and an 11th straight quarter of triple-digit AI growth — but profitability collapsed under the reinvestment, adjusted EBITA down 84 percent and free cash flow swinging to a RMB17.3 billion outflow as management reiterated it will overshoot the RMB380 billion plan, citing a roughly 10x increase in data-centre needs versus 2022 (Alibaba FY2026 Q4 · F1059).
ByteDance is now the most aggressive scaling buyer, and it is partly internalising its demand. In May 2026 it revised its 2026 capex plan up to over RMB200 billion (about USD29 billion), a roughly 25 percent increase on its initial ~RMB160 billion guidance, citing higher AI-infrastructure investment and rising memory-chip costs — leaving it outspending the prior big-three combined, with its Doubao assistant at 345 million MAU and over 120 trillion daily token calls driving the build (ByteDance · F1055). Even stacked together, China’s three big cloud buyers plan only ~$60-80B of 2026 AI capex (mixing single-year budgets, an annualized slice of Alibaba’s 3-year ~$53B pledge, and Tencent’s total capex) against the US Big-4’s ~$725B — under 1/10, with Amazon (~$200B) alone outspending all of China roughly 3x, which is why Beijing engineers a captive order book it cannot win on market scale (valueaddvc · F1278; US Big-4 · F1257). It also co-designs a 5nm AI ASIC with Broadcom (TSMC-fabbed, export-compliant), began its own SeedChip accelerator with TSMC in 2024, and is reportedly developing custom inference CPUs — the economic driver being a roughly 30-50 percent lower total cost of ownership than Nvidia GPUs on fixed internal workloads (Reuters/industry · F981). Tencent, long the conservative outlier on a pre-acquired GPU stockpile and an efficiency-first path, reversed course in early 2026: after cutting quarterly capex to about RMB13.0 billion in Q3 2025, it spent RMB31.9 billion in Q1 2026, up 63 percent quarter-on-quarter, with strategy chief James Mitchell pledging a substantial 2026 increase (especially in H2) as more China-designed chips become available, and Goldman Sachs modelling RMB165 billion of Tencent capex by 2027 — more than double 2025 levels (Tencent Q1-2026 · F1065). Even “hyperscaler demand,” then, is three strategies — scale out, internalise, and now re-accelerate — converging on the same domestic-silicon offtake. For all that, the four Chinese CSPs remain dwarfed by their US peers: TrendForce’s May-2026 forecast for the top-nine cloud providers’ 2026 capex of about USD830 billion has ByteDance (~USD29 billion), Alibaba (~USD19 billion) and Tencent (~USD12 billion 2025 base) as a small fraction of the aggregate — the demand-side scale gap that pushes Beijing toward mandates rather than market scale (TrendForce · F1070).
Figure — China’s three big cloud buyers plan ~$60-80B of 2026 capex
(basis varies: Tencent figure is total capex with a smaller AI slice;
Alibaba is an annualized cut of a 3-yr ~$53B pledge) against the US
Big-4’s ~$725B — under 1/10, with Amazon (~$200B) alone ~3x all of
China. The ~1/10 ratio holds either way. Source: valueaddvc/ByteDance-Alibaba-Tencent
· F1278; US
Big-4 · F1257.
Beneath the capex sits the workload that pulls it. By end-2025, more than 600 million users in China engaged with generative-AI tools, up about 142 percent year-on-year (Technology.org/IndexBox · F862). Cheap, efficient open models turn that user base into enormous inference-token volume — exactly the workload where domestic accelerators are most competitive. The clearest single trigger was the DeepSeek V4 release on 24 April 2026, explicitly optimised for Huawei Ascend: ByteDance, Tencent and Alibaba all reopened Ascend talks the same day, and the demand surge pushed Huawei chip prices up about 20 percent (Reuters/SCMP · F981). The constraint is supply, not demand: the Ascend 950PR began mass production in April 2026, but Huawei plans to ship only about 750,000 950PR units in 2026 (total Ascend family ~1.6 million dies), capped by a lack of advanced fab tools — and ByteDance alone has committed to spend over USD5.6 billion on Ascend chips in 2026, from near zero (Reuters/SCMP · F981; Ascend ramp · F37). The H200 episode shows the demand bottleneck flipping sides. In May 2026 the US Commerce Department cleared about ten Chinese firms — Alibaba, Tencent, ByteDance and others — to buy Nvidia H200 chips, capped at 75,000 units each, under a framework taking a 25 percent US revenue cut; but Beijing declined to let them buy, with the central government steering investment to domestic industry, and no deliveries had occurred by mid-2026 (CNBC · F1146). The binding demand constraint on Nvidia in China is now Chinese self-reliance policy, not US licensing — channelling the order book straight to Ascend, Cambricon and Hygon (Reuters/Igor’s Lab · F1196).
Both Nvidia chips and domestic accelerators reach hyperscaler and state buyers through a small set of server integrators. By IDC’s H1 2025 ranking, the top three China AI-server vendors by revenue — Inspur, H3C and Lenovo — together took nearly 50 percent of the market; by shipment volume, Inspur, H3C and Ningchang held about 43 percent (IDC · F855). This channel is the physical chokepoint for the localisation push. Its defining feature is that the volume is enormous and the margin is paper-thin.
| Server OEM (channel) | FY2025 revenue | Margin signal | Source |
|---|---|---|---|
| Inspur (浪潮信息, 000977) | RMB164.78bn (~USD23bn), +43.25% | Net profit only RMB2.413bn (+5.2%); overall gross margin 4.77%, server gross margin 4.52% | Inspur FY2025 AR · F895 |
| H3C (新华三, via Unisplendour) | RMB75.98bn, +37.96% | Group gross margin fell from 19.8% (2022) to 14.4% (H1 2025) as AI-server mix grew | Unisplendour FY2025 · F978 |
| xFusion (超聚变) | ~RMB58.2bn (from RMB43.5bn/USD6.1bn in 2024) | Net margins 1-2% (2023-2025); R&D and sales costs ate most gross profit | xFusion IPO prospectus · F859 |
Inspur shows the pattern most sharply. It is the global No.2 and China No.1 server vendor, with over 50 percent of China’s AI-server share and core compute supply to ByteDance, Alibaba, Tencent and the three telcos. Yet FY2025 net profit rose only 5.2 percent on 43 percent revenue growth — the classic 增收不增利 (revenue up, profit flat) signature of a low-margin integration layer (Inspur FY2025 AR · F895). Its RMB19.51 billion of contract liabilities points to an order backlog the channel cannot yet fill (Inspur FY2025 AR · F895). H3C’s compute segment (AI servers and clusters) added RMB9.46 billion of H1 revenue year-on-year even as group gross margin compressed (Unisplendour FY2025 · F978), and xFusion — spun out of Huawei’s x86 server business and now China No.1 in liquid-cooled and AI servers — runs at 1-2 percent net margins (xFusion IPO prospectus · F859). The OEM channel is where state demand becomes physical systems, but it captures almost none of the value. That value accrues upstream, to the accelerator and memory makers — which is exactly why the capital wave in Section 3 chases the silicon, not the boxes.
If demand is concentrated, the capital behind it is concentrated by design. Primary Chinese registry data confirm that the China National Integrated Circuit Industry Investment Fund Phase III (大基金三期) was registered on 24 May 2024 with RMB344 billion (3,440亿元) of capital — about USD47.5 billion, larger than Phases I and II combined (CSRC/中证网 · F708; Caixin · F7). For scale: Phase I (2014) ultimately raised RMB138.7 billion and Phase II (2019) registered RMB204.15 billion, so Phase III roughly equals the two prior phases stacked together (CSRC/中证网 · F708). The Ministry of Finance is the largest shareholder at RMB60 billion (17.44 percent), and six state banks contributed RMB114 billion (33.14 percent) — the first commercial-bank participation in any Big Fund phase (CSRC/中证网 · F708). For comparison, the entire US CHIPS Act direct-incentive pool is about USD39 billion, smaller than Phase III alone (CETAS · F158).
Figure 2 — Big Fund III’s RMB344 billion roughly equals Phases I and
II stacked together. Source: CSRC/中证网
· F708.
That scale cuts both ways, and the chart should be read alongside the record in Section 4: the Big Fund’s own leadership was jailed in a graft probe (Caixin · F556), and the local-government layer it sits atop produced the Wuhan Hongxin (武汉弘芯) zombie fab — a roughly USD19 billion (RMB128 billion) planned 14nm/7nm project that made zero chips before the local government took it over (talent/fraud record · F-Chiang). The largest chequebook in the world is also the one with the largest documented misallocation.
Phase III is aimed squarely at the chokepoints earlier phases left unsolved. It began deploying in January 2025 through two intermediary sub-funds — RMB71 billion into Guotou Jixin and RMB93 billion into Huaxin Dingxin — with stated priorities of wafer manufacturing, equipment and materials, and AI; the broader plan targets lithography machines, photoresists, advanced packaging and HBM specifically (CETAS/36Kr · F158). By mid-2025 it had reportedly reoriented toward concentrated breakthroughs in domestic lithography and EDA after the May 2025 US ban on the three EDA majors, with analysts estimating it aims to lift equipment localisation from under 25 percent (excluding lithography) to over 40 percent within five years (analyst estimate · F841). Deployment is slow and indirect, though. The first publicly disclosed direct deal came only in September 2025 — up to RMB450 million into Piotech’s hybrid-bonding unit — and no cumulative deployment total is public (Tom’s Hardware/Caixin · F621). The largest deployment to date surfaced in early January 2026, when SMIC announced a USD7.778 billion capital increase into SMIC South (its 14nm-and-below advanced-node entity), bringing in Big Fund Phase III alongside six state banks; Big Fund III alone added USD1.832 billion of the stake, and combined with a same-day USD5.79 billion buyout of SMIC North minorities the moves lifted SMIC South’s registered capital toward USD10.1 billion — a direct state-financed push behind SMIC’s role as Huawei’s exclusive Ascend foundry (SMIC/TrendForce · F1100).
Where that capital lands shows up as physical wafer capacity, and the trajectory — not the point-in-time stock — is the part the bars elsewhere miss. China’s installed capacity rose from 310 msi of silicon area in 2018 to about 631 msi in 2024 and a projected 875 msi by 2029, while total wafer capacity climbed about 15 percent to 8.85 million wafers/month in 2024 and a further 14 percent to roughly 10.1 million wpm in 2025 — China adding more new capacity in 2024 than the rest of the world combined (TechInsights/SEMI · F695). Its share of global capacity is rising on two distinct bases that should not be conflated: by total wafer capacity (all device types, including memory and IDM) China was about 21 percent in 2024, level with Taiwan and Korea, and is forecast at roughly 30 percent by 2030; by foundry-only capacity, IDC projects China overtakes Taiwan as the world’s largest foundry base by 2028, reaching about 37 percent versus Taiwan’s 35 percent and the US’s 8 percent by 2029 (TechInsights · F695; IDC/BusinessNext · F577). The flow of net new capacity has tipped to China even while it still trails on installed stock — the clearest composition shift in the build-out, and the physical thing all the state capital above is buying.
Figure — China’s absolute wafer capacity keeps climbing (310 → 631 →
875 msi; 8.85M → 10.1M wpm) while two distinct share measures rise on
their own denominators — total wafer-capacity share ~21 percent (2024) →
~30 percent (2030E) and foundry-only share to 37 percent by 2029E,
overtaking Taiwan. The two share lines are NOT one trend; each states
its base. Source: TechInsights/SEMI
· F695; IDC/BusinessNext
· F577.
The cheque is amplified by mandates that manufacture demand. By late 2025, MIIT (with NDRC input) issued unofficial guidance setting a 50 percent domestic-tool target for new fab build-outs, with proposals below that threshold typically rejected — a forcing function that pulls demand toward domestic toolmakers (Reuters · F321). By February 2026 that floor was being lifted toward a roughly 70 percent domestic-equipment target by 2027, alongside concrete tool progress — SMEE 28nm immersion systems in verification, Naura 28nm etch in mass production (TrendForce · F1174). On the chip side, the Xinchuang (信创) IT-localisation programme — enforced through SASAC’s Document 79, which requires central SOEs and party-government bodies to complete foreign-hardware and software replacement by 2027 — now mandates domestic AI chips, with Huawei Ascend and Cambricon added to the procurement list in 2025 (US-China Business Council · F541). In May 2026, nine categories of domestically designed AI chips — from Huawei, Alibaba’s T-Head, Biren and Moore Threads — cleared a government security review, formalising the approved-vendor list for state and security-sensitive deployment; Huawei, having shipped about 812,000 Ascend chips in 2025, is the chief beneficiary and projects about USD12 billion of AI-processor revenue in 2026 (roughly +60 percent) (SCMP/TechTimes · F1129). Behind it sits the structural prize: a drafted roughly USD295 billion (RMB2 trillion) NDRC national compute grid carrying an 80 percent-domestic mandate and a 2028 target, which writes Nvidia and AMD out of the largest new compute procurement on earth — a key reason Nvidia’s share of China’s AI-chip market has fallen to effectively zero from about 95 percent in 2022, with zero Data Center Hopper shipments to China in the quarter ending April 2026 (versus USD4.6 billion a year earlier) (TechTimes · F1135). China Telecom’s localisation ramp shows the effect in tenders already let: the locally produced share of its annual server tender rose from 20 percent (2020) to nearly 50 percent (2024) to 67.5 percent (2025) (state-demand record · F906).
Against a decade-long backdrop, the absolute spend is the largest in the world. CSIS estimated China’s semiconductor industrial-policy spending at about USD142 billion between 2014 and 2023 — roughly 3.6 times the USD39 billion the US committed over the same window. State the ratio as a range, since it depends on which windows are paired: ~$142B (CSIS, 2014-2023) against the US CHIPS Act’s ~$52.7B authorized or ~$39B in direct grants is ~2.7-3.6x — and the US figure is direct appropriations only, excluding the 25% investment tax credit and private capex, so this measures state-cheque size, not total capital mobilized (CSIS via Tom’s Hardware · F1279; Big Fund III · F708). The CSIS figure also predates Big Fund III (CSIS via Tom’s Hardware · F-CSIS). The import bill dwarfs every one of these state-funding numbers: China spent ~$385B importing integrated circuits in 2024 — its single largest import, bigger than crude oil (~$325B) — roughly 7x the US CHIPS Act and ~2.5x its own cumulative decade of subsidies, leaving a ~$226B annual chip trade deficit that sizes why self-sufficiency is existential, not aspirational (SCMP · F1274; IC exports · F553). The Semiconductor Industry Association frames cumulative Chinese support as well over USD150 billion across 2014-2030 (SIA · F-SIA).
Figure — The most arresting reframe of why self-sufficiency is
existential: China spent ~$385B importing chips in 2024 — its #1 import,
bigger than crude oil (~$325B) — ~7x the US CHIPS Act and ~2.5x its own
cumulative decade of fab subsidies, leaving a ~$226B annual chip trade
deficit. Source: SCMP
· F1274; CSIS
subsidy estimate · F1279.
The chequebook’s scale is matched by a record of misallocation that money alone cannot fix. From mid-2022, anti-graft regulators investigated the Big Fund’s own leadership for “severe violations of discipline,” targeting in particular Huaxin Investment (华芯投资), the sole trustee-manager of Phases I and II (TechNode · F311). The probe reached prosecution. Lu Jun, former CEO of the trustee-manager, was expelled from the Party in January 2023 and indicted on bribery charges in March 2024 (Caixin · F556); fund president Ding Wenwu and VP Ren Kai — who oversaw the SMIC, CXMT and YMTC investments — were placed under investigation in 2022, with verdicts undisclosed (Caixin · F556). The heaviest sentence landed on Zhao Weiguo, ex-chairman of Big-Fund-linked Tsinghua Unigroup, who received a suspended death sentence in May 2025 for corruption and embezzlement (Caixin · F556). Beijing’s response was a governance redesign, not a retreat: Phase III excludes Huaxin entirely, splits decisions across four general partners, and runs 15 years to 2039 — a direct answer to the graft saga (Tianyancha/巨潮 · F551).
Beneath the fund sits the cautionary case: the local-government layer. Big Fund Phase I produced clear winners — SMIC, YMTC, Hua Hong, Sanan, JCET — but also notable failures, with local funds wasting billions on projects whose founders had no chip experience (Phase I record · F326). The emblem is Wuhan Hongxin (HSMC, 武汉弘芯), an ambitious 14nm/7nm-aspirant fab carrying a planned RMB128 billion (about USD19 billion) budget that recruited TSMC veteran Chiang Shang-yi as CEO in 2019. It was later exposed as a multi-billion-RMB fraud that produced zero chips, left engineers and builders unpaid, and was taken over by the local government in November 2020 (talent/fraud record · F-Chiang). A marquee name did not save it from being an empty-fab fraud — the clearest illustration that state money chasing capacity targets without underlying capability buys announcements, not output.
Where Big Fund money goes early, the public market re-rates it later — often spectacularly. The pre-IPO cap tables of the GPU “four little dragons” (四小龙) — Moore Threads, MetaX, Biren and Enflame — are dominated by provincial and municipal guidance funds and national-team vehicles. The state is the pre-IPO capital layer, and the day-one IPO pop is where that value crystallises for public markets (STCN/36Kr · F1012). The December 2025 STAR debuts produced some of the largest first-day moves in the market’s history.
| Vendor | Pre-IPO valuation | IPO / day-one outcome | Source |
|---|---|---|---|
| MetaX (沐曦) | RMB21.07bn (Mar-2025 final round) | Raised RMB4.2bn (~USD594M) at RMB104.66 issue, closed +693-700% on debut; >RMB300B day-one cap; priced 50x 2024 sales; Q1-2026 revenue +75% YoY | CNBC · F691; SCMP · F1103 |
| Moore Threads (摩尔线程) | RMB24.62bn (pre-IPO pre-money) | Dec-5-2025 debut ~4,000x oversubscribed, +468% day one; H1-2025 revenue RMB700M but cumulative losses RMB5.2bn since 2022, profitability only targeted 2027; +425% vs offer; 2026 shipment target ~500k vs ~116k in 2025 | TrendForce · F814; SCMP · F1103 |
| Biren (壁仞) | ~RMB14bn (~USD2bn, pre-HK) | HK IPO HK$5.58bn (USD717M) at top of range; popped +76% to ~USD10.6bn cap | TrendForce/Douglas · F814 |
| Enflame (燧原) | ~USD2.8bn (Hurun, pre-IPO) | SSE cleared 15-Jun-2026, targeting RMB6bn (~USD888M), listing H2-2026; revenue RMB990M (2025); cumulative losses ~RMB4.29bn; Tencent both top holder (~20.26%) and ~84% of 2025 revenue | Bloomberg · F61; Hurun/SSE · F982 |
The valuation math is the point. MetaX priced at 50x its 2024 sales — against 34x for Nvidia and 14x for AMD — and was, per KPMG, China’s sixth-biggest IPO of the year (CNBC · F691). These multiples sit far above Western peers even though the companies are loss-making: Moore Threads and MetaX alone have racked up over RMB80 billion in combined losses since 2022, and a fund manager called the surge a likely five-year peak and an explicit “pre-IPO arbitrage” (CNBC · F691). The gap between last private rounds (RMB14-25 billion) and day-one public caps (RMB300 billion-plus) quantifies that arbitrage — and the lock-up overhang that follows (TrendForce · F814). The pre-profit door is widening, not narrowing: on 17 June 2026 China extended the STAR Market’s fifth listing standard — about RMB4 billion market cap, government certification of core technology, no profitability requirement — to loss-making large-model and quantum firms, while CSRC officials simultaneously warned they would punish theme-driven hyping, threading the line between opening the IPO pipeline and curbing the very AI-equity speculation the cohort embodies (CSRC/TechTimes · F1112).
The benchmark for the whole tier is Cambricon, the only profitable, listed China AI-accelerator. Its private-placement issue price jumped roughly 10x, from RMB121.1 in 2023 to RMB1,195.02 in October 2025 (Cambricon filings · F991), and Q1 2026 revenue reached RMB2.88 billion (about USD400 million, +160 percent — roughly equal to all of H1 2025) with net profit RMB1.01 billion (+185 percent, more than double Q4 2025) and gross margin above 54 percent, on ByteDance and Alibaba anchor demand; on 30 April 2026 it regained China’s most-valuable-stock (股王) status at a market cap above RMB710 billion (~USD100 billion), and it targets 500,000 accelerator shipments in 2026 against ~116,000 in 2025 (Cambricon Q1-2026 · F1050). The other procurement-list winner, Hygon (海光信息), posted FY2025 revenue of RMB14.38 billion (+56.9 percent) and net profit RMB2.54 billion (+31.7 percent), guiding Q1 2026 revenue up 63-76 percent, and by mid-June 2026 traded at a ~USD101 billion market cap (~190x P/E) — even after the proposed RMB116 billion Hygon-Sugon reverse merger, which would have created a 400-billion-yuan compute giant, was terminated in December 2025 when Sugon’s share price surged and opened a valuation gap (Hygon FY2025 · F1073; merger collapse · F1106). The largest IPO of the cohort is in memory: CXMT cleared the STAR listing committee on 27 May 2026 and received CSRC IPO-registration approval on 15 June 2026, targeting about RMB29.5 billion (~USD4.2 billion) — the second-largest STAR IPO ever after SMIC’s RMB53.23 billion — with proceeds earmarked RMB13 billion for a Phase-II fab, RMB7.5 billion for line upgrades and RMB9 billion for next-gen DRAM R&D (CXMT/SCIO · F1038). The state value the listing crystallises is now visible in the financials: CXMT FY2025 revenue was RMB61.8 billion (+155.6 percent) and Q1 2026 revenue RMB50.8 billion (+over 7x year-on-year) with net profit RMB33.0 billion, powered by the global DRAM super-cycle (CXMT IPO prospectus · F1037).
Every dollar of capital and every captive order eventually hits the same wall: people. MIIT and CSIA framed a structural integrated-circuit workforce gap that widened to about 300,000 in H1 2024 (a roughly 25 percent year-on-year rise), with over 60 percent of unmet demand in core R&D and manufacturing rather than design. China graduates only about 30,000 IC-major students a year against a 2020 total-demand estimate near 720,000 (MIIT/CSIA · F566). By 2025 the gap had widened, not closed: one supply-demand series put it near 1,000,000 with a roughly 50 percent gap rate, while a CSIA-cited core-engineering figure held at 300,000-plus. SMIC founder Richard Chang (Zhang Rujing) repeatedly framed the gap at about 300,000, stressing that the scarcest talent is not PhDs but frontline industrial craftsmen, on a training cycle of five years to minor competence and ten to major (talent record · F881; Richard Chang · F611). In an April 2026 Ningbo lecture he reiterated that the gap is still widening — the CSIA core figure rising from about 250,000 missing professionals in 2022 to about 300,000 by 2025 — but reframed the binding problem as a skills mismatch rather than raw headcount: the localisation pivot stranded commodity-role workers while domestic-equipment-engineer vacancies now stretch 120-180 days to fill, and executives at SEMICON China 2026 conceded China lags 5-10 years in automotive and data-centre semiconductors, with retention a key constraint (Shanghai 75 percent, Shenzhen 70 percent, Wuhan only 65 percent) (Zhang Rujing/DigiTimes · F1152).
The frontier runs on imported human capital. The structural reason China cannot close the senior gap at home is that its most elite STEM talent is trained in, and overwhelmingly retained by, the US. The value mirror frames why the gap persists where it does: by company headquarters, US-HQ firms book ~50% of global chip sales from ~1/5 of consumption, while China is the largest IC importer (~$385B) yet captures only ~12-14% of value-added — the inverse, concentrated exactly in the leading-edge logic, HBM and EUV tools China still imports (SIA Factbook · F1281; SCMP imports · F1274). Per CSET using NSF data, about 90 percent of Chinese nationals who completed US STEM PhDs in 2000-2015 were still in the US as of February 2017, with intention-to-stay rates of 85-90 percent (CSET · F731). The returnee channel that does exist is thin and constrained. China quietly revived its Thousand Talents Plan under the low-profile name Qiming (启明), recruiting in sensitive fields including semiconductors with RMB3-5 million signing bonuses, but actual flows are small — one county reported that only 8 of the prior year’s successful candidates actually returned — and the October 2022 US-person rule added legal risk for dual-status scientists (Reuters/CSET · F626). Yet the returnee top-slice is load-bearing where it lands. The leading-edge memory effort depends on returnees at the very top: CXMT president Cao Kanyu is a UC Berkeley PhD who built its DRAM roadmap from zero, and SemiAnalysis frames CXMT’s progress as supplied by returnees from US memory majors plus contested Korea hires (SemiAnalysis · F905m).
Retention, not just recruitment, is the measured weakness at the leading edge. Per SMIC ESG disclosures, overall employee turnover was 21.22 percent in 2021 and 16.94 percent in 2022 — against TSMC’s 6.8 percent and 6.7 percent — and SMIC’s 2018 figure of 22 percent was roughly 5x TSMC’s then (SMIC ESG · F766). The marquee retention episode is Liang Mong Song, the ex-TSMC and ex-Samsung process veteran who led SMIC to 14nm and 28nm volume production. When the board recruited Chiang Shang-yi as vice chairman in December 2020 without consulting him, his resignation threat circulated online, SMIC halted Hong Kong trading, and the A-share fell about 7-9 percent intraday — a price tag on how key-person-dependent the foundry is (SMIC 2020 AR/TechNews · F686). To keep him, SMIC raised his 2020 compensation to RMB28.811 million (from about RMB2.23 million the prior year), including a gifted property worth RMB22.5 million, then granted him 400,000 restricted shares in 2021 (SMIC 2020 AR · F686). Equity is the sector’s primary lock-in instrument — by mid-2021, semiconductor firms accounted for over 20 percent of all listed-company equity-incentive plans — but even grants of about RMB9 million do not guarantee retention, as the July 2020 walk-away of FinFET technologist Wu Jingang showed (equity-incentive record · F806). The instability reaches the very top: the Chiang-Liang turf conflict — two ex-TSMC stars recycled across rival PRC projects — is itself a talent-stability risk at China’s most advanced foundry (talent record · F-Chiang).
Demand is real but state-shaped, not market-discovered. A market doubling to about USD16 billion in H1 2025, with China server revenue at USD19.2 billion in Q1 2026 alone and heading past USD140 billion by 2029 on the fastest CAGR in the world (IDC/InfotechLead · F1194), is large, but about 69 percent of it is four hyperscalers (IDC/Caixin · F858) and the rest is floored by procurement mandates that now reach an 80 percent-domestic national compute grid and have driven Nvidia’s China AI-chip share to effectively zero (TechTimes · F1135). This is a guaranteed order book for domestic silicon — precisely what capability-building needs in order to amortise. Capability comes first, then a demand curve the state can point at it.
The capital is the largest on earth and explicitly aimed at the chokepoints. Big Fund III’s RMB344 billion exceeds Phases I and II combined, and the US CHIPS direct pool (CSRC/中证网 · F708; CETAS · F158), targeting lithography, photoresist, HBM and packaging — the same gaps the supply-side dives identify. Its largest visible deployment landed in January 2026, a USD7.78 billion SMIC South capital increase that put Big Fund III directly behind Huawei’s exclusive Ascend foundry (SMIC/TrendForce · F1100). Money is not the binding constraint.
But money has repeatedly bought announcements rather than chips. The graft probe jailed the fund’s own leadership (Caixin · F556) and the Wuhan Hongxin fraud produced zero chips (talent/fraud record · F-Chiang) — direct evidence that pouring capital at capacity targets before capability exists is how the failures happened. The Phase III governance redesign concedes the point.
The IPO wave prices in success that has not yet been earned. MetaX at 50x sales versus Nvidia’s 34x (CNBC · F691), on companies with RMB80 billion-plus of combined losses, is the market crystallising state pre-IPO value — and the door is widening, with Enflame cleared in June 2026 (Bloomberg · F61), CXMT’s ~USD4.2 billion memory listing registered the same month (CXMT · F1038), and the STAR fifth standard newly extended to loss-making model and quantum firms (F1112). It is a re-rating of the investment narrative that runs ahead of demonstrated capability, and that fund managers themselves call a peak and an arbitrage.
The channel captures little; the value is upstream. Inspur, H3C and xFusion run AI-server businesses at 1-5 percent margins (Inspur FY2025 · F895; xFusion · F859), which is why both the capital and the thesis point upstream to accelerators and memory, not the box-builders.
Talent is the constraint capital cannot relax on demand. The 300,000-to-1,000,000 gap is widening, and by April 2026 the binding problem had reframed as a skills mismatch — domestic-equipment-engineer roles taking 120-180 days to fill, China still 5-10 years behind in automotive and data-centre chips (Zhang Rujing/DigiTimes · F1152; talent record · F881). The frontier depends on a thin slice of US-trained returnees (CSET · F731), and SMIC’s roughly 3x-TSMC turnover plus the Liang retention saga (SMIC ESG/2020 AR · F766; F686) show that the human input gates how fast any of the capital or demand turns into chips. It is the cleanest case that capability, not investment, is the leading variable.
The cleanest way to invest in China’s drive for semiconductor self-sufficiency is to stop chasing household names and instead score each candidate on two axes: exposure (how directly it is leveraged to the localization buildout) and purity (how much of its value comes from that buildout rather than from cyclical or speculative demand). Ranked on exposure times purity, the best longs are the profitable “picks-and-shovels” pure-plays — the equipment, materials, and EDA (electronic design automation, the software used to design chips) national champions that sit in front of a captive, policy-directed pool of demand (SEMI/Yole · F714). Below them sit the capacity foundries (high exposure, low margin), then the loss-making AI-accelerator IPOs (a large addressable market, but valuations built on dreams), and finally the foreign chokepoint holders China must keep buying from even as it tries to displace them (TrendForce · F595). The thesis pays off when you own the picks-and-shovels, treat the foundries as a cyclical capacity bet, treat the accelerators as policy and momentum beta rather than value, and accept that several of the most strategic names cannot be bought at all.
Figure 1 — Rank by exposure times purity: the profitable equipment,
materials, and EDA pure-plays (Tier 1) sit top-right, where the
localization tailwind is most binding and the play is cleanest; the
AI-accelerator IPOs (Tier 3) share the high binding but at low purity
and high risk. Source: CSIS/CSET
· F707.
Captive demand for tools is the structural foundation of the trade. In 2024 China was roughly 40% of global spending on wafer-fab equipment (WFE) — about USD 41B, per Yole — yet only about 5% of that equipment is made in China (SEMI/Yole · F714). On a broader measure that includes all equipment, not just WFE, SEMI put China’s 2024 investment at a record ~USD 49.5B, the single largest market ahead of Korea (~20% of global purchases), Taiwan (10-20%), and the US (~10%); China’s total equipment market then held at ~USD 49.3B in 2025 (+23% on the broad measure, ~43% of global), with 2026 demand inflecting further on CXMT/YMTC memory expansion (Yole/EW · F1200). The supply side is closing the gap: China’s overall equipment-localization rate rose from 8% in 2021 to 23.2% in 2025, projected at ~39% by 2030 — a shift from policy-driven to performance-driven competitiveness — but it stays a staircase by category, with back-end test now ~40% local and front-end metrology/inspection still the weakest link under 10% (Yole/EW · F1200). The gap between roughly 40% of demand and a still-small share of supply is the entire import-substitution opportunity, and two policy levers are mobilizing it: a roughly 50% domestic-tool procurement mandate and the third national semiconductor fund, Big Fund III (CSIS/DBS/CSET · F268).
Big Fund III (大基金三期, RMB 344B / USD 47B, operating from 31 December 2024) signals where state capital flows (Eurasia Review · F626). It marks a deliberate pivot. Phase II (2019, ~USD 29B) put roughly 75% into wafer-fab capacity; Phase III concentrates instead on the upstream chokepoints — lithography, inspection, etch, deposition, and 3D-integration tools, plus EDA, photoresists, specialty gases, silicon wafers, and power modules — to insulate fabs from foreign restrictions (Eurasia Review · F626). Initial deployment routed about RMB 93B (USD 12.7B) into materials and equipment makers, and the first publicly disclosed direct deal (September 2025) was up to RMB 450M into Piotech’s 3D hybrid-bonding unit (Eurasia Review · F626). For investors, this confirms that the money is concentrating in the picks-and-shovels tier, not commodity capacity.
CSIS and CSET map the equipment landscape as a “staircase” that sets exposure and purity by category, not by company (CSIS/CSET · F707). Front-end WFE domestic share rose to about 21% in 2024, up from 10% in 2021; back-end assembly, test, and packaging went from 19% to 36% (CSIS/CSET · F707).
| Category | China status | Best-positioned listed name | Tier read |
|---|---|---|---|
| Photoresist strip + cleaning | Winning, 50%+ local | ACM Research (688082) | Long |
| Etch | 30-35% (FY25), heading to 40-45% | AMEC (688012), NAURA (002371) | Long |
| Thin-film deposition / CMP / thermal | Advancing fast | NAURA, Piotech, Anji (CMP slurry) | Long |
| Lithography (EUV + ArF immersion) | Hard chokepoint, foreign-locked | SMEE (private) vs ASML | Too early / higher-risk |
| Metrology / inspection | Hard chokepoint | Skyverse (688361) vs KLA | Higher-binding, lumpier |
| Ion implantation, track (coat/develop), high-end materials | Hard chokepoints | — | Foreign-locked |
Source: (CSIS/CSET · F707)
The investment implication is precise. The purest, most defensible longs sit where China is both winning and demand is captive: etch, deposition, cleaning, and CMP slurry (the consumable used in chemical-mechanical polishing). Metrology and lithography bind harder — they are deeper chokepoints — but they are earlier-stage and riskier. The runway is long but uneven. The Made-in-China-2025 target of 70% self-sufficiency was badly missed: against the broad equipment measure China sourced about 23% locally in 2025, on track toward only ~39% by 2030 (Yole/EW · F1200).
Figure 2 — China missed both Made-in-China-2025 self-sufficiency
targets (the 70% goal was later deleted from the 15th Five-Year Plan),
and a single self-sufficiency number is uninterpretable without its
denominator — the same year spans a ~4x range. Source: TechInsights/CSIS
· F1004; Nikkei/kr-asia
· F729; assembled ·
F1289.
This tier is the cleanest expression of the thesis: equipment, materials, and EDA national champions that are profitable under standard accounting and backed by Big Fund III capital, the domestic-tool mandate, and captive demand. China was 42% of global semiconductor manufacturing equipment spending in 2024, against a target to raise tool self-sufficiency from about 20% to 50-60% by 2030 (CSIS/DBS/CSET · F268).
Equipment. NAURA Technology (北方华创, 002371) is the flagship and the only Chinese name in the global WFE top six (behind ASML, AMAT, Lam, TEL, and KLA), having risen to world No. 6 in 2024 from No. 8 in 2023 (DigiTimes · F467). Its etch-equipment localization rate jumped from 12% in 2019 to 58% in 2024, and it supplies about 60% of the oxidation and diffusion furnaces serving SMIC’s 28nm production (iTiger · F266). FY2025 results (reported April 2026) confirm the scale-up but flag the margin-quality tension: revenue hit a record RMB 39.35B (+30.85%), yet net profit slipped 1.77% (增收不增利) as R&D rose 34.74% to RMB 7.28B (18.5% of revenue); Q1-2026 revenue was RMB 10.32B (+25.80%) with net profit up only 3.42%, though gross margin rebounded +3.6pp QoQ to 40.77% and operating cash flow swung positive (NAURA filing · F1089). NAURA is also pushing up the staircase: in March 2026 it launched 12-inch wafer-to-wafer and chip-to-wafer hybrid-bonding tools (HBM/chiplet advanced packaging) and took control of coater-developer (track) leader Kingsemi (芯源微), so the two firms now cover over 97% of the wet-process flow; 2026 company revenue guidance is RMB 46.79-52.02B (NAURA filing · F1097; NAURA filing · F1080).
| Name (ticker) | Market cap | Fwd P/E | Note |
|---|---|---|---|
| NAURA (002371) | ~USD 68.2B (Jun-26) | ~42.7x | Only Chinese name in WFE top-6; FY25 rev RMB 39.35B (+30.85%), Q1-26 RMB 10.32B (+25.80%) |
| AMEC (688012) | ~USD 15.2B | ~34.9x | Etch + MOCVD specialist; Q1-26 net profit +~200% YoY |
| ACM Research A (688082) | ~USD 1.44B | — | Cleaning leader; Q1-26 rev USD 231.3M (+34.2%) |
| Skyverse (688361) | — | — | Metrology/inspection vs KLA; Q1-26 rev RMB 396M (+34.6%), net loss -RMB 68M on R&D push |
Source: NAURA Q1-2026 (NAURA filing · F1080); AMEC (AMEC filing · F1104); ACM (ACM 10-Q · F1133); Skyverse (Skyverse filing · F1160); valuation baseline (late-May 2025, DBS/Bloomberg/CMBI) (DBS/CMBI · F694)
The Q1-2026 prints confirm a genuine earnings inflection across the tier. AMEC’s net profit grew nearly 200% YoY on high-end etch volume (advanced-logic mid-stage and UHAR memory etch in mass production) plus a one-off gain from trimming its Piotech stake, and it is acquiring CMP-tool maker Hangzhou Zhonggui to add wet/CMP and metrology to its dry-etch base (AMEC filing · F1104; AMEC/SSE · F1113). Piotech (拓荆科技, 688072) itself swung to a Q1-2026 net profit of RMB 571M from a year-earlier loss as deposition tools scaled, though much of that was non-recurring fair-value gains (扣非 net only ~RMB 102M) (Piotech filing · F1119). ACM Research’s consolidated Q1-2026 revenue rose 34.2% to USD 231.3M with FY2026 guidance reaffirmed at USD 1.08-1.175B (ACM 10-Q · F1133). The standout sub-sector in 2025-2026 was back-end test: Changchuan (300604, FY2025 net profit +190%, Q1-2026 +218%) and Accotest (688200, FY2025 net profit +60%) both compound far faster than the front-end toolmakers as OSAT and SoC/CIS capacity expands (Changchuan filing · F1147; Accotest filing · F1151). Skyverse is the higher-risk metrology bet: Q1-2026 revenue grew 34.6% but it ran a -RMB 68M loss on a deliberate R&D surge (+52% to 46% of revenue), with the order book the tell — contract liabilities jumped 55.8% QoQ to RMB 881M as its overlay metrology and dark-/bright-field defect-inspection tools won batch validation at top logic and memory customers (Skyverse filing · F1160).
Materials are the higher-quality slice. Anji Microelectronics (安集科技, 688019) is among the purest picks-and-shovels plays: 2024 revenue of RMB 1.84B (+48.24% year over year), net income of RMB 533.64M, and global polishing-slurry share up from 7% in 2022 to 11% in 2024 (TECHCET/broker · F621). The ramp continued: Anji revenue is tracked at RMB 2.47B for 2025 rising to a forecast RMB 3.18B for 2026, gross margins holding ~57-58% as it extends into electroplating (ECP) chemistries and advanced nodes (reportify · F1099). Because the product is a consumable, sold per wafer on a recurring basis, materials carry far better margins than the price-warring equipment names, though Anji still imports key abrasives (silica sol, fumed silica) from Japan and the US (reportify · F1099). The mandate-named materials peers sit in the same bucket, but the localization is uneven within CMP: slurry is the most advanced front, while domestic CMP pads still meet under 30% of Chinese demand in 2026, with Hubei Dinglong (300054) the lead pad supplier qualified at fabs including YMTC for mature-node CMP (reportify · F1099).
EDA. Empyrean (华大九天, 301269) and Primarius (概伦电子, 688206) bind hard, because EDA below 7nm is a deep chokepoint, but they are priced on price-to-sales rather than P/E because heavy R&D and equity-incentive costs suppress reported earnings (EET-China/broker · F677). Empyrean’s FY2025 company filing confirms a ~RMB 44.9B market cap on revenue of RMB 1.325B (+8.40%) but net profit of only RMB 61M (-44.30%), as R&D reached 64.84% of revenue (~60% directed at digital EDA); Q1-2026 then swung to a -RMB 73M loss on licensing seasonality and research headcount, even as its digital-EDA flow coverage reached nearly 80% with a full-link target now slipped to 2027 (Empyrean filing · F1179). Primarius is smaller but turned a corner: FY2025 revenue rose 15.41% to RMB 484M with net profit of RMB 34.24M, swinging to profit from a prior-year RMB 96M loss — both all-time highs since its 2021 listing — though Q1-2026 returned to a small (mostly non-recurring) loss at an 86.21% gross margin (Primarius filing · F1186). China’s domestic EDA localization is now ~17-23% and rising more than 50% a year, but the split persists: analog-chip EDA has passed 30% and is deployable at 28nm-plus, while high-end digital (emulation, formal verification, timing, synthesis, physical implementation) remains under 15% and still depends almost entirely on Synopsys, Cadence, and Siemens (ofweek · F1189). Both names benefit from the May-2025 US EDA cutoff and the consolidation that followed, though the scorecard is mixed: Primarius is the live consolidator, executing its ~RMB 2.174B acquisition of Chengdu Actt plus 45.64% of Nanon Micro to become a one-stop EDA-plus-IP platform, while Empyrean terminated its flagship Xpeedic deal in July 2025 (Primarius filing · F1186; DigiTimes · F820). The competitive backdrop hardened further: after the US lifted the EDA curbs, China’s SAMR cleared Synopsys’s USD 35B acquisition of Ansys in Q3-2025 on conditions that protect Chinese customers’ contracts, treating advanced EDA as a strategic dependency even amid the thaw (SCMP · F1177).
Tier 1 carries a specific risk: aggressive domestic price competition, amplified by the procurement mandates, is compressing gross margins at the leading toolmakers. NAURA fell from 43.8% in 2022 to 41.4% in 2025; AMEC from 45.83% in 2023 to 39.17% in 2025; ACM from 51.9% in 2023 to 48.3% in 2025; and Piotech sharply, from 49.3% in 2022 to 33.3% in 2025 (The Economy · F267). Government adoption directives lift short-term sales but fuel overlapping investment and discount-driven competition (The Economy · F267). The early-2026 prints show the compression is not yet a one-way street — NAURA’s gross margin rebounded +3.6pp QoQ to 40.77% and Piotech’s recovered to 41.69% as advanced-process tools scaled — but R&D and equity-incentive intensity keep net margins thin even as revenue compounds (NAURA filing · F1089; Piotech filing · F1119). At roughly 40x P/E, NAURA already prices in years of share gains, so the margin trajectory is the thing to watch (DBS/CMBI · F694).
SMIC (0981.HK / 688981) and Hua Hong (1347.HK / 688347) are the capacity-tier plays: directly leveraged to the fab buildout, but structurally lower-margin and exposed to mature-node commodity risk. Both draw roughly 88% of revenue from China, yet through 2025 a mature-node oversupply and price war crushed profitability (DigiTimes/AInvest · F648). The cycle inflected by Q1-2026: SMIC posted revenue of USD 2,505M (RMB 17.62B, +8.1% YoY), gross margin 20.1%, and net profit of USD 197M, then guided Q2-2026 revenue up a well-above-consensus 14-16% QoQ to USD 2.85-2.9B at 20-22% gross margin; Hua Hong swung harder, with Q1-2026 net profit up 458% YoY to USD 20.9M on a 13% gross margin and a Q1 beat that lifted shares ~12% (SMIC earnings · F1084; Hua Hong filing · F1188).
| Metric (Q1-2026 unless noted) | SMIC | Hua Hong |
|---|---|---|
| Gross margin | 20.1% (Q2 guide 20-22%) | 13.0% (FY25 11.8%, up from 10.2%) |
| Net profit | USD 197M (+0.4% YoY) | USD 20.9M (+458% YoY) |
| Revenue | USD 2,505M (+8.1% YoY); Q2 guide +14-16% QoQ | USD 660.9M (+22.2% YoY); Q2 guide USD 690-700M |
| Capex | ~USD 8.1B FY2026 (≈flat); depreciation +~30% YoY | USD 924.9M (mostly 12-inch); 12-inch now 62.7% of rev |
| Utilization | 93.1% (-2.6pt QoQ) | — |
Source: SMIC Q1-2026 (SMIC earnings · F1084), capex/depreciation guidance (SMIC call · F1145); Hua Hong Q1-2026 (Hua Hong filing · F1188)
The bull case turned in late 2025 and into 2026, as TSMC and Samsung vacated mature nodes, lifting utilization and enabling roughly 10% price hikes on BCD, power, and CIS chips into 2026 (DigiTimes/AInvest · F648); an “AI siphon” — leading foundries pivoting to AI/HBM — is now redirecting standard and specialty orders to SMIC and Hua Hong (SMIC call · F1145). The valuation gap is the other leg: SMIC trades near 15x P/E against TSMC’s 25-30x. But the bear case is real — depreciation now eats ~44 cents of every SMIC sales dollar (up from ~37-38% a year earlier) and is guided +~30% in 2026, capacity additions are actually slowing to ~40k 12-inch-equivalent wafers/month because early-bought litho lacks matching support tools (长短脚 mismatch), and the roughly 100% US-tariff threat and Section 301 scrutiny make this a lower-purity, higher-cyclicality slice than Tier 1 (SMIC call · F1145; SMIC earnings · F1176). The state keeps funding through it: in January 2026 SMIC took a USD 7.778B capital increase into SMIC South — its 14nm-and-below entity — bringing in Big Fund III alongside six state banks, underscoring its role as Huawei’s exclusive Ascend foundry (SMIC filing · F1100). The same capacity tier extends to the winning device families flagged in the brief — SiC/GaN power (Innoscience, StarPower, SiLan, CR Micro, Sanan, SICC), CMOS image sensors (OmniVision, SmartSens, GalaxyCore), and OSAT packaging (JCET, TongFu, SJSemi) — where Hua Hong’s BCD, power, and CIS price hikes are the read-through (DigiTimes/AInvest · F648).
The December-2025 IPO wave centered on China’s “four little dragons” of GPUs — Moore Threads, MetaX, Biren, and Enflame — alongside the already-listed Cambricon (CNBC · F691). By mid-2026 the cohort is fully listed: Moore Threads (5-Dec-2025 STAR debut) and MetaX listed first, Biren took the Hong Kong route in late December 2025, and Enflame — the last of the four — cleared its STAR review on 15 June 2026 for a ~RMB 6B raise (Tencent owns ~20% and supplied ~84% of 2025 revenue) (SCMP · F1103). Baidu’s Kunlunxin is now queued behind them, pursuing a dual Hong Kong / STAR listing with 2024 revenue already over RMB 1B (nai500 · F1132). These are large-market names trading on price-to-sales multiples far above Western peers — but the tier has bifurcated sharply on fundamentals. Cambricon is now decisively profitable and pulling away from the loss-making cohort; read the IPO challengers as policy and momentum beta, and Cambricon increasingly as the one earnings story.
| Name (ticker) | Status / cap (2026) | Valuation flag | Profitability |
|---|---|---|---|
| Cambricon (688256) | ~RMB 710B+ (~USD 100B); regained 股王 Apr-2026 | ~250-348x trailing P/E | Profitable: Q1-26 rev RMB 2.88B (+160%), net RMB 1.01B (+185%) |
| Hygon (688041) | ~USD 101B cap; Sugon reverse-merger terminated Dec-2025 | ~38x EV/Rev, ~190x P/E | Profitable; 2nd procurement-list name (CPU + DCU) |
| Moore Threads (688795) | Dec-5-25 STAR debut +468%; ~+425% vs offer | ~123x 2024 sales | Loss-making; ~RMB 5.2B cumulative loss, profit targeted 2027 |
| MetaX (688802) | IPO raised RMB 4.2B; +700% debut; ~RMB 41.9B val. | 50x 2024 sales vs Nvidia 34x | Loss-making; Q1-26 rev +75% YoY |
| Biren (HK) | late-Dec-25 HK listing, trades above offer | H1-25 rev ~RMB 58.9M vs ~RMB 1.6B loss | Loss-making; Entity-Listed Oct 2023 |
| Enflame (688795 STAR) | cleared 15-Jun-2026 for ~RMB 6B raise | Tencent ~20% owner, ~84% of 2025 rev | Loss-making; ~RMB 4.29B cumulative loss |
Sources: Cambricon (Cambricon earnings · F1050, Caixin · F813); Hygon (multiples.vc · F1094); the four dragons (SCMP · F1103); MetaX/Moore Threads (CNBC · F691); Biren (Yahoo · F716); Kunlunxin (nai500 · F1132)
Cambricon’s turn is the single biggest change in this tier. Q1-2026 revenue of RMB 2.88B (+160% YoY) roughly matched all of H1-2025, net profit hit RMB 1.01B (+185%), operating cash flow turned positive, and on 30 April 2026 the stock hit its daily limit at RMB 1,700 with single-session turnover over RMB 26B, regaining 股王 status at a market cap above RMB 710B (~USD 100B) (Cambricon earnings · F1050). It targets ~500,000 accelerator shipments in 2026 (roughly triple ~116-142k in 2025), gated by SMIC 7nm yield (~20%) — the same fab ceiling that limits Huawei Ascend (Tom’s Hardware · F1182). The structural driver is policy: Cambricon and Huawei are the only two names on China’s government-approved AI-hardware procurement list, so state and SOE buyers are channeled to them while the IPO challengers compete for the remaining (largely hyperscaler) demand (Yahoo · F1199). Hygon (海光信息, 688041) — CPU plus DCU GPGPU and the second name on that list — trades independently again after the ~RMB 116B Hygon-Sugon reverse-merger was terminated in December 2025, carrying a ~USD 101B cap at ~190x P/E on +54% revenue growth (multiples.vc · F1094). The forward narrative is priced at a multiple of the actual global leader: Moore Threads at ~123x sales and Cambricon at ~250-348x P/E trade well above Nvidia (~34x sales) and AMD (~14x sales) — Nvidia being the world’s most valuable chipmaker with >$190B in annual Data Center revenue and ~90% AI-accelerator share (CNBC · F691; Nvidia · F1256).
Figure 3 — China’s AI-accelerator names trade at a
forced-substitution premium, not comparable cash generation: their P/S
multiples run 1.5-3.5x the global leaders, and Nvidia carries the lowest
multiple despite the largest revenue. Source: KrAsia/Reuters
· F582; Real
Time Mandarin · F585; CNBC
· F1282.
The valuation backdrop is still extreme. The SSE STAR Chip index traded near 118x earnings in late 2025, against just ~12x for the broad Shanghai Composite — a near-tenfold premium that reflects forced-substitution demand and the self-sufficiency narrative rather than current cash flows (Reuters/Yahoo · F583). Even against an already AI-inflated US semis basket the premium is stark — the STAR Chip ~118x is ~2.7x the iShares Semiconductor ETF’s ~43x TTM — though the trailing multiple is distorted upward by loss-making STAR constituents, so the gap is wider still on a forward basis where many domestic AI names have little or no earnings (SOXX TTM P/E · F1276). Cambricon is the cautionary precedent: at its 2020 IPO its price-to-sales peaked between 200x and 300x, then corrected sharply once sentiment cooled, only re-rating when AI demand rebounded (Reuters · F585). Fund managers called the Moore Threads and MetaX debuts a likely “peak for the next five years” and a pre-IPO arbitrage; the gap between the last private rounds (RMB 14-25B) and day-one public caps (RMB 300B+) quantifies that arbitrage (CNBC · F691, TrendForce · F814). And the IPO door is being widened deliberately: on 17 June 2026 China extended the STAR Market’s pre-profit fifth listing standard to loss-making large-model (LLM) and quantum firms (only a ~RMB 4B market cap and government tech-certification required, no profit), while regulators simultaneously warned they would punish theme-driven hyping — the structural enabler for the next wave of unprofitable AI listings (TechTimes · F1112). These firms are also throttled by limited high-bandwidth-memory (HBM) supply and were founded almost entirely by ex-Nvidia and ex-AMD returnees, so the moat is people and policy, not yet earnings (restofworld · F797). The software moat that gates these names is being slowly eroded by generative-AI kernel generation but not closed — generated kernels still reach only ~40% of an expert’s performance, and the tool’s data/tooling flywheel favors the CUDA incumbent at least as much — so treat it as a modest, asymmetric tailwind, not a re-rating catalyst (CUDABench · F1221; see D8 §9). The re-rating has since spread beyond compute to optical interconnect: Yuanjie Semiconductor (源杰科技, 688498) overtook Moutai as the 股王 in April 2026 before Cambricon reclaimed it, underscoring that this is a momentum trade rotating across the AI-hardware supply chain (TrendForce/SCMP · F838).
The mirror image of the long is a structural short on the foreign incumbents whose tools China still cannot replace at advanced nodes, but whose China revenue is eroding. A mid-2025 cross-section ranked China revenue share at TEL 34%, Lam 31%, ASML 27%, KLA 26%, and Applied Materials 25%; these five together still ship roughly USD 25-30B+ of equipment to China per year, even as the controls bite (TrendForce · F595). The trajectory is clearly down, and the latest prints show it accelerating. Applied Materials’ China revenue fell from USD 10.12B (37.2% of the total) in FY2024 to USD 8.53B (30.1%) in FY2025 (TrendForce · F595). ASML is the sharpest move: China fell to just 19% of net system sales in Q1-2026, down from 36% in Q4-2025, as Dutch DUV controls and a stockpiling reversal bit — South Korea (45%) overtook China as ASML’s largest market for the first time (Bloomberg · F1064). The squeeze is set to tighten further: the Netherlands shifted ASML’s license-filing for certain tools to Dutch authority effective 1 April 2026, and the bipartisan MATCH Act — which cleared a House committee markup on 22 April 2026 — would ban even ASML DUV-immersion sales to Chinese chipmakers and bar servicing of installed machines (Tom’s Hardware · F1093; Asia Times · F1074). These names remain the levered short on China localization, yet still draw a fifth to a third of revenue from the very buildout they are restricted from fully serving.
The EDA Big 3 are the same story in software. Synopsys (~31% global share), Cadence (~30%), and Siemens EDA (~13%) hold more than 85% combined — the binding chokepoint China cannot yet replace at advanced nodes (TrendForce · F603). In FY2024, Synopsys earned about USD 1B from China (~16% of revenue) and Cadence about USD 550M (~12%). The May-2025 license requirement sent Synopsys shares down 9.6% and Cadence down 10.7% in a day before the controls were lifted in July 2025, and Synopsys’s ex-Ansys China revenue fell about 22% in FY2025 as Empyrean and Primarius captured mature-node share (TrendForce · F603). By Q1-2026 the China line had stabilized at a lower plateau rather than collapsing: Cadence reported China at 13% of revenue and guided 12-13% for FY2026 (vs 13% of FY2025), even as it raised overall FY2026 growth guidance to ~17% (Cadence · F1192). The enforcement risk is now concrete, not theoretical: in April 2026 BIS reached a settlement in which Cadence admitted its China subsidiary knowingly transferred US technology to Entity-Listed military-linked parties (NUDT, Phytium), the administrative complement to its July-2025 DOJ guilty plea and ~USD 140.6M penalty (CRS · F1198).
Nvidia is the purest example of the policy-engineered transfer that underwrites the domestic-accelerator long. Before the April-2025 H20 ban, China was about 17% of Nvidia’s data-center revenue (~USD 7-8B a year), and Nvidia held about 95% of China’s advanced-AI-accelerator market; CEO Jensen Huang said that share collapsed to “0%” (Tom’s Hardware · F607). By mid-2026 that collapse is confirmed and structural: China fell to ~5.9% of Nvidia revenue in Q2 FY2026 (vs a ~15% average over the prior ten quarters) and to 13% of FY2025 (from 21% in FY2023), and the filing for the quarter ending April 2026 reported zero Data Center Hopper shipments to China, against USD 4.6B a year earlier (Nvidia filing · F1071). The December-2025 thaw has not reversed it: Commerce cleared ~10 Chinese firms (Alibaba, Tencent, ByteDance) to buy H200 (capped 75,000 units each, with a 25% revenue cut to the US government), but as of mid-2026 no H200 deliveries had occurred, blocked by legal limbo and Beijing’s own rule barring foreign AI chips from state-funded datacenters (builtin · F1066). The drafted ~USD 295B NDRC national compute grid (80%-domestic mandate, 2028 target) would structurally write Nvidia out of the largest new compute procurement globally — a forced gift of share to Huawei and Cambricon (TechTimes · F1135). Separately, China’s market regulator (SAMR) opened an antitrust investigation into Nvidia in September 2025; as of mid-2026 it remained at the preliminary-finding stage (Nvidia found not to have fully honored remedies from its 2020 Mellanox approval), with no final penalty issued but exposure of up to 10% of prior-year China sales (~USD 17B base) still on the table (Xinhua · F573; Mondaq · F1118).
A core caveat: several of the most strategically central names cannot be bought, and the IPOs that can be bought are largely inaccessible to foreigners at debut. YMTC (China’s largest NAND maker, about 11.8% of global NAND in 2024) is unlisted and carries a December-2022 blanket Entity-List ban; Huawei is wholly employee-owned and offers outside investors only bonds; US persons are barred from dealing with YMTC and CXMT (Wikipedia/CSIS · F651). The most strategic pre-IPO value sits with state vehicles — SiCarrier is wholly owned by a Shenzhen-SASAC entity and raised about USD 2.8B at an ~USD 11B valuation privately — so an IPO is the only liquidity event for foreign capital, and even then the state allocates to national strategy, not risk-adjusted returns (EET-China/composite · F822).
CXMT (长鑫存储) is the partial exception and the marquee 2026 capital-markets event. It won STAR Market approval for what is shaping up as China’s biggest-ever chip listing, raising about RMB 29.5B (~USD 4.2-4.4B); revenue grew from RMB 8.29B in 2022 to RMB 61.8B in 2025, with a first net profit of RMB 1.88B, and Q1-2026 revenue jumped over 7x year over year (profit nearly 17-fold) on the global DRAM shortage (Caixin/Bloomberg · F851; CryptoBriefing · F1122). Proceeds fund DRAM capacity (SemiAnalysis estimates ~257k wafers/month in 2026, just under 15% of global DRAM) plus an HBM3 build-out, with HBM yield-conversion the constraint (CryptoBriefing · F1122). The pipeline is broadening behind it: CSRC chair Wu Qing confirmed both CXMT and YMTC are lining up domestic listings, and the first embodied-AI listing (Unitree Robotics) cleared the STAR committee on 1 June 2026 (KraneShares · F1204). Even so, foreign retail investors are effectively shut out of STAR IPOs: Stock Connect does not cover freshly listed stocks, northbound eligibility arrives only several months after listing and only for institutional professional investors, and direct participation requires the institutional QFII/RQFII scheme (CNBC · F760, Deacons · F904). For ADR-based exposure, the HFCAA delisting tail-risk re-armed under the February-2025 America First memo, which is why HK dual or primary listings — the route chosen by Biren, Kunlunxin, and SMIC — are the structural hedge; notably ~85% of 2026 China AI IPOs (23 of 27) chose Hong Kong, the internationally-oriented route, while state-linked firms favor the mainland (White & Case · F803; KraneShares · F1204).
Synthesizing exposure, purity, policy-binding, and earnings quality (CSIS · F713):
| Tier | Description | Names | Earnings | Verdict |
|---|---|---|---|---|
| 1 | Purest pick-and-shovel, profitable | NAURA, AMEC, ACM, Piotech, Hwatsing, Kingsemi, Skyverse (equipment); Anji, Dinglong, Jiangfeng (materials); Empyrean, Primarius (EDA) | Profitable (EDA P/S-valued) | Core long — best binding x purity; watch margins & ~40x P/E |
| 2 | Capacity, leveraged but commodity-risk | SMIC, Hua Hong; SiC/GaN & CIS device families | Thin/cyclical margins | Cyclical capacity bet — utilization & price-hike driven |
| 3 | AI-accelerator IPO wave | Moore Threads, MetaX, Biren, Enflame, Kunlunxin (loss-making); Cambricon, Hygon (now profitable, procurement-list) | Mixed: IPO cohort loss-making; Cambricon/Hygon profitable | Policy/momentum beta, not value — P/S on dreams; Cambricon now the one earnings story |
| 4 | The other side / not-investable | ASML, AMAT, Lam, TEL, KLA, Synopsys, Cadence, Nvidia (eroding); YMTC, Huawei, pre-IPO CXMT (cannot buy) | n/a | Structural short / no access |
Source: (CSIS · F713)
The bottom line: the payoff in China’s semiconductor self-sufficiency drive accrues first and most cleanly to the profitable picks-and-shovels (Tier 1), is a cyclical capacity bet at the foundries (Tier 2), is speculative policy beta at the AI accelerators (Tier 3), and is a structural short plus an access wall on the other side (Tier 4). Rank by exposure times purity, weight toward earnings quality, and the decision is straightforward.